Gitiles
Code Review Sign In
review.coreboot.org / coreboot / c9d9729f5cd80b29427e94b7ab91faaaa54d17db / . / src / mainboard / intel / kunimitsu / gpio.h
blob: 0dbf7826a39798fe0b4c331372262ab5bd39f343 [file] [log] [blame]
Lee Leahyc4210412015-06-29 11:37:56 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
Lee Leahyb993d2f2015-07-17 11:07:54 -0700[diff] [blame]18 * Foundation, Inc.
Lee Leahyc4210412015-06-29 11:37:56 -0700[diff] [blame]19 */
20
robbie zhangc9d97292015-08-21 09:47:34 -0700[diff] [blame^]21#ifndef MAINBOARD_GPIO_H
22#define MAINBOARD_GPIO_H
Lee Leahyc4210412015-06-29 11:37:56 -0700[diff] [blame]23
24#include <soc/gpio.h>
25
robbie zhangc9d97292015-08-21 09:47:34 -0700[diff] [blame^]26static const struct pad_config gpio_table[] = {
27/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
28/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
29/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
30/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
31/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
32/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
33/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
34/* PIRQA# */ /* GPP_A7 */
35/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
36/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
37/* PCH_LPC_CLK */ /* GPP_A10 */
38/* EC_HID_INT */ /* GPP_A11 */
39/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 0, DEEP),
40/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
41/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
42/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
43/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
44/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
45/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
46/* ISH_GP1 */ /* GPP_A19 */
47/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
48/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
49/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
50/* ISH_GP5 */ /* GPP_A23 */
51/* CORE_VID0 */ /* GPP_B0 */
52/* CORE_VID1 */ /* GPP_B1 */
53/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
54/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP),
55/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP),
56/* SRCCLKREQ0# */ /* GPP_B5 */
57/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
58/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
59/* SRCCLKREQ3# */ /* GPP_B8 */
60/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
61/* SRCCLKREQ5# */ /* GPP_B10 */
62/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
63/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
64/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
65/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
66/* GSPI0_CS# */ /* GPP_B15 */
67/* WLAN_PCIE_WAKE */ PAD_CFG_GPI(GPP_B16, NONE, DEEP),
68/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
69/* GSPI0_MOSI */ /* GPP_B18 */
70/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
71/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
72/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
73/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
74/* SM1ALERT# */ /* GPP_B23 */
75/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
76/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
77/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
78/* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP),
79/* SML0DATA */ /* GPP_C4 */
80/* SML0ALERT# */ /* GPP_C5 */
81/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
82/* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP),
83/* UART0_RXD */ /* GPP_C8 */
84/* UART0_TXD */ /* GPP_C9 */
85/* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP),
86/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 1, 20K_PD, DEEP),
87/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
88/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
89/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
90/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
91/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
92/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
93/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
94/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
95/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
96/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
97/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),
98/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
99/* ITCH_SPI_CS */ /* GPP_D0 */
100/* ITCH_SPI_CLK */ /* GPP_D1 */
101/* ITCH_SPI_MISO_1 */ /* GPP_D2 */
102/* ITCH_SPI_MISO_0 */ /* GPP_D3 */
103/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
104/* EN_PP3300_DX_EMMC */ PAD_CFG_GPO(GPP_D5, 1, DEEP),
105/* EN_PP1800_DX_EMMC */ PAD_CFG_GPO(GPP_D6, 1, DEEP),
106/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
107/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
108 PAD_CFG_GPO(GPP_D9, 0, DEEP),
109/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP),
110/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 1, DEEP),
111/* EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_D12, 1, DEEP),
112/* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP),
113/* ISH_UART0_TXD */ /* GPP_D14 */
114/* ISH_UART0_RTS */ /* GPP_D15 */
115/* ISH_UART0_CTS */ /* GPP_D16 */
116/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
117/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
118/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
119/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
120/* ITCH_SPI_D2 */ /* GPP_D21 */
121/* ITCH_SPI_D3 */ /* GPP_D22 */
122/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
123/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP),
124/* SATAXPCIE1 */ /* GPP_E1 */
125/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
126/* CPU_GP0 */ /* GPP_E3 */
127/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
128/* SATA_DEVSLP1 */ /* GPP_E5 */
129/* SATA_DEVSLP2 */ /* GPP_E6 */
130/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP),
131/* SATALED# */ /* GPP_E8 */
132/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
133/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
134/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
135/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
136/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
137/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
138/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
139/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
140/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
141/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
142/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
143/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
144/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
145/* DDPD_CTRLCLK */ PAD_CFG_GPI(GPP_E22, NONE, DEEP),
146/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
147/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
148/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
149/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
150/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
151/* I2C2_SDA */ /* GPP_F4 */
152/* I2C2_SCL */ /* GPP_F5 */
153/* I2C3_SDA */ /* GPP_F6 */
154/* I2C3_SCL */ /* GPP_F7 */
155/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
156/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
157/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
158/* I2C5_SCL */ /* GPP_F11 */
159/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
160/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
161/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
162/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
163/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
164/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
165/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
166/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
167/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
168/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
169/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
170 /* GPP_F23 */
171/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
172/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
173/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
174/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
175/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
176/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
177/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
178/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
179/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
180/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
181/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
182/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
183/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
184/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
185/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
186 /* GPD7 */
187/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
188/* PCH_SLP_WLAN# */ /* GPD9 */
189/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
190/* LANPHYC */ /* GPD11 */
Lee Leahyc4210412015-06-29 11:37:56 -0700[diff] [blame]191};
192#endif