Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corporation |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Lee Leahy | b993d2f | 2015-07-17 11:07:54 -0700 | [diff] [blame] | 18 | * Foundation, Inc. |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 19 | */ |
| 20 | |
Naveen Krishna Chatradhi | fac5eb0 | 2015-06-24 21:56:57 +0530 | [diff] [blame] | 21 | #ifndef _MAINBOARD_GPIO_H_ |
| 22 | #define _MAINBOARD_GPIO_H_ |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 23 | |
| 24 | #include <soc/gpio.h> |
| 25 | |
Naveen Krishna Chatradhi | fac5eb0 | 2015-06-24 21:56:57 +0530 | [diff] [blame] | 26 | const GPIO_INIT_CONFIG mainboard_gpio_table[] = { |
| 27 | //Primary Well Group A |
| 28 | /* EC_PCH_RCIN */ |
| 29 | { GPIO_LP_GPP_A0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 30 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 31 | /* LPC_LAD_0 */ |
| 32 | { GPIO_LP_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 33 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 34 | /* LPC_LAD_1 */ |
| 35 | { GPIO_LP_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 36 | GpioOutDefault, GpioIntDis, GpioTermNone} }, |
| 37 | /* LPC_LAD_2 */ |
| 38 | { GPIO_LP_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 39 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 40 | /* LPC_LAD_3 */ |
| 41 | { GPIO_LP_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 42 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 43 | /* LPC_FRAME */ |
| 44 | { GPIO_LP_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 45 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 46 | /* LPC_SERIRQ */ |
| 47 | { GPIO_LP_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, |
| 48 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 49 | /* XDP_PREQ */ |
| 50 | { GPIO_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 51 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 52 | /* LPC_CLKRUN */ |
| 53 | { GPIO_LP_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, |
| 54 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 55 | /* EC_LPC_CLK */ |
| 56 | { GPIO_LP_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 57 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 58 | /* PCH_LPC_CLK */ |
| 59 | { GPIO_LP_GPP_A10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 60 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 61 | /* EC_HID_INT */ |
| 62 | { GPIO_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 63 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 64 | /* ISH_KB_PROX_INT */ |
| 65 | { GPIO_LP_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 66 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 67 | /* PCH_SUSPWRACB */ |
| 68 | { GPIO_LP_GPP_A13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 69 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 70 | /* PM_SUS_STAT */ |
| 71 | { GPIO_LP_GPP_A14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 72 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 73 | /* PCH_SUSACK */ |
| 74 | { GPIO_LP_GPP_A15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 75 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 76 | /* SD_1P8_SEL */ |
| 77 | { GPIO_LP_GPP_A16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 78 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 79 | /* SD_PWR_EN */ |
| 80 | { GPIO_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, |
| 81 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 82 | /* GYRO INTERRUPT */ |
| 83 | { GPIO_LP_GPP_A18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 84 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 85 | /* ALS INTERRUPT / SNSR_HUB_INT */ |
| 86 | { GPIO_LP_GPP_A19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 87 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 88 | /* ISH_GYRO_DRDY/ACCEL INTERRUPT */ |
| 89 | { GPIO_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 90 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 91 | /* SNSR_HUB_STANDBY_WAKE */ |
| 92 | { GPIO_LP_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 93 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 94 | { GPIO_LP_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 95 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 96 | { GPIO_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 97 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 98 | //Primary Well Group B |
| 99 | |
| 100 | { GPIO_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 101 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 102 | { GPIO_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 103 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 104 | /* HSJ_MIC_DET */ |
| 105 | { GPIO_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 106 | GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 107 | /* TRACKPAD_INT */ |
| 108 | { GPIO_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 109 | GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep, |
| 110 | GpioTermNone} }, |
| 111 | /* BT_RF_KILL */ |
| 112 | { GPIO_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 113 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 114 | { GPIO_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 115 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 116 | /* WIFI_CLK_REQ */ |
| 117 | { GPIO_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 118 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 119 | /* KEPLR_CLK_REQ/VIDEO_CLK_REQ */ |
| 120 | { GPIO_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 121 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 122 | { GPIO_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 123 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 124 | /* SSD_CLK_REQ/CLK_REQ_SSD */ |
| 125 | { GPIO_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 126 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 127 | { GPIO_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 128 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 129 | /* MPHY_EXT_PWR_GATE */ |
| 130 | { GPIO_LP_GPP_B11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 131 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 132 | /* PM_SLP_S0 */ |
| 133 | { GPIO_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 134 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 135 | /* PCH_PLT_RST */ |
| 136 | { GPIO_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 137 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 138 | { GPIO_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 139 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 140 | /* WWAN_DISABLE */ |
| 141 | { GPIO_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 142 | GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 143 | /* WLAN_PCIE_WAKE */ |
| 144 | { GPIO_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 145 | GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 146 | /* SSD_PCIE_WAKE */ |
| 147 | { GPIO_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 148 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 149 | { GPIO_LP_GPP_B18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 150 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 151 | /* CCODEC_SPI_CS */ |
| 152 | { GPIO_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 153 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 154 | /* CODEC_SPI_CLK */ |
| 155 | { GPIO_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 156 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 157 | /* CODEC_SPI_MISO */ |
| 158 | { GPIO_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 159 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 160 | /* CODEC_SPI_MOSI */ |
| 161 | { GPIO_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 162 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 163 | { GPIO_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 164 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 165 | //Primary Well Group C |
| 166 | /* SMB_CLK */ |
| 167 | { GPIO_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 168 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 169 | /* SMB_DATA */ |
| 170 | { GPIO_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 171 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 172 | { GPIO_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 173 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 174 | /* M2_WWAN_PWREN */ |
| 175 | { GPIO_LP_GPP_C3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 176 | GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 177 | { GPIO_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 178 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 179 | { GPIO_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 180 | GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 181 | /* EC_IN_RW */ |
| 182 | { GPIO_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 183 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 184 | /* USB_CTL */ |
| 185 | { GPIO_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 186 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 187 | { GPIO_LP_GPP_C8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 188 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 189 | { GPIO_LP_GPP_C9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 190 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 191 | /* NFC_RST* */ |
| 192 | { GPIO_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 193 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 194 | /* EN_PP3300_KEPLER */ |
| 195 | { GPIO_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 196 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K} }, |
| 197 | /* PCH_MEM_CFG0 */ |
| 198 | { GPIO_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 199 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 200 | /* PCH_MEM_CFG1 */ |
| 201 | { GPIO_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 202 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 203 | /* PCH_MEM_CFG2 */ |
| 204 | { GPIO_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 205 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 206 | /* PCH_MEM_CFG3 */ |
| 207 | { GPIO_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 208 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 209 | /* I2C0_SDA */ |
| 210 | { GPIO_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 211 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpu5K} }, |
| 212 | /* I2C0_SCL */ |
| 213 | { GPIO_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 214 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpu5K} }, |
| 215 | /* I2C1_SDA */ |
| 216 | { GPIO_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 217 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 218 | /* I2C1_SCL */ |
| 219 | { GPIO_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 220 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 221 | /* GD_UART2_RXD */ |
| 222 | { GPIO_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 223 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 224 | /* GD_UART2_TXD */ |
| 225 | { GPIO_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 226 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 227 | /* TCH_PNL_PWREN */ |
| 228 | { GPIO_LP_GPP_C22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 229 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 230 | /* SCREW_SPI_WP_STATUS */ |
| 231 | { GPIO_LP_GPP_C23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 232 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K} }, |
| 233 | |
| 234 | // Primary Well Group D |
| 235 | /* ITCH_SPI_CS */ |
| 236 | { GPIO_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 237 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 238 | /* ITCH_SPI_CLK */ |
| 239 | { GPIO_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 240 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 241 | /* ITCH_SPI_MISO */ |
| 242 | { GPIO_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 243 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 244 | /* CAM_FLASH_STROBE */ |
| 245 | { GPIO_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 246 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 247 | /* EN_PP3300_DX_EMMC */ |
| 248 | { GPIO_LP_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 249 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 250 | /* EN_PP1800_DX_EMMC */ |
| 251 | { GPIO_LP_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 252 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 253 | /* SH_I2C1_SDA */ |
| 254 | { GPIO_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 255 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 256 | /* SH_I2C1_SCL */ |
| 257 | { GPIO_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 258 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 259 | { GPIO_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 260 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 261 | /* USB_A0_ILIM_SEL */ |
| 262 | { GPIO_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 263 | GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 264 | /* USB_A1_ILIM_SEL */ |
| 265 | { GPIO_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 266 | GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 267 | /* EN_PP3300_DX_CAM */ |
| 268 | { GPIO_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 269 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 270 | /* EN_PP1800_DX_AUDIO */ |
| 271 | { GPIO_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 272 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 273 | /* WWAN_WAKE* */ |
| 274 | { GPIO_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 275 | GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 276 | { GPIO_LP_GPP_D15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 277 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 278 | { GPIO_LP_GPP_D16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 279 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 280 | /* DMIC_CLK_1 */ |
| 281 | { GPIO_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 282 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 283 | /* DMIC_DATA_1 */ |
| 284 | { GPIO_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 285 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 286 | /* DMIC_CLK_0 */ |
| 287 | { GPIO_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 288 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 289 | /* DMIC_DATA_0 */ |
| 290 | { GPIO_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 291 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 292 | /* ITCH_SPI_D2 */ |
| 293 | { GPIO_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 294 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 295 | /* ITCH_SPI_D3 */ |
| 296 | { GPIO_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 297 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 298 | /* I2S_MCLK */ |
| 299 | { GPIO_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 300 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 301 | //Primary Well Group E |
| 302 | /* SPI_TPM_IRQ */ |
| 303 | { GPIO_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 304 | GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 305 | { GPIO_LP_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 306 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 307 | /* SSD_PEDET */ |
| 308 | { GPIO_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 309 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 310 | { GPIO_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, |
| 311 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 312 | { GPIO_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, |
| 313 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 314 | { GPIO_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 315 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 316 | /* SSD_SATA_DEVSLP */ |
| 317 | { GPIO_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 318 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 319 | /* TCH_PNL_INTR* */ |
| 320 | { GPIO_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 321 | GpioOutDefault, (GpioIntApic | GpioIntLevel), |
| 322 | GpioResetDeep, GpioTermNone} }, |
| 323 | { GPIO_LP_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 324 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 325 | /* USB2_OC_0 */ |
| 326 | { GPIO_LP_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 327 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 328 | /* USB2_OC_1 */ |
| 329 | { GPIO_LP_GPP_E10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 330 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 331 | /* USB2_OC_2 */ |
| 332 | { GPIO_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 333 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 334 | /* USB2_OC_3 */ |
| 335 | { GPIO_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 336 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 337 | /* DDI1_HPD */ |
| 338 | { GPIO_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 339 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 340 | /* DDI2_HPD */ |
| 341 | { GPIO_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 342 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 343 | /* EC_SMI */ |
| 344 | { GPIO_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 345 | GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 346 | /* EC_SCI */ |
| 347 | { GPIO_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 348 | GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 349 | /* EDP_HPD */ |
| 350 | { GPIO_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 351 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 352 | { GPIO_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 353 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 354 | { GPIO_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 355 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 356 | { GPIO_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 357 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 358 | { GPIO_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 359 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 360 | { GPIO_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 361 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 362 | /* TCH_PNL_RST */ |
| 363 | { GPIO_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, |
| 364 | GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 365 | //Primary Well Group F |
| 366 | /* I2S2_SCLK */ |
| 367 | { GPIO_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, |
| 368 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 369 | /* I2S2_SFRM */ |
| 370 | { GPIO_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, |
| 371 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 372 | /* I2S2_TXD */ |
| 373 | { GPIO_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 374 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 375 | /* I2S2_RXD */ |
| 376 | { GPIO_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 377 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 378 | { GPIO_LP_GPP_F4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 379 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 380 | { GPIO_LP_GPP_F5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 381 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 382 | { GPIO_LP_GPP_F6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 383 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 384 | { GPIO_LP_GPP_F7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 385 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 386 | /* I2C4_SDA */ |
| 387 | { GPIO_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 388 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 389 | /* I2C4_SDA */ |
| 390 | { GPIO_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 391 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 392 | /* AUDIO_IRQ */ |
| 393 | { GPIO_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 394 | GpioOutDefault, GpioIntApic | GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 395 | /* AUDIO_SW_INT* */ |
| 396 | { GPIO_LP_GPP_F11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, |
| 397 | GpioOutDefault, GpioIntApic | GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 398 | /* EMMC_CMD */ |
| 399 | { GPIO_LP_GPP_F12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 400 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 401 | /* EMMC_D_0 */ |
| 402 | { GPIO_LP_GPP_F13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 403 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 404 | /* EMMC_D_1 */ |
| 405 | { GPIO_LP_GPP_F14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 406 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 407 | /* EMMC_D_2 */ |
| 408 | { GPIO_LP_GPP_F15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 409 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 410 | /* EMMC_D_3 */ |
| 411 | { GPIO_LP_GPP_F16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 412 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 413 | /* EMMC_D_4 */ |
| 414 | { GPIO_LP_GPP_F17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 415 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 416 | /* EMMC_D_5 */ |
| 417 | { GPIO_LP_GPP_F18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 418 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 419 | /* EMMC_D_6 */ |
| 420 | { GPIO_LP_GPP_F19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 421 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 422 | /* EMMC_D_7 */ |
| 423 | { GPIO_LP_GPP_F20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 424 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 425 | /* EMMC_RCLK */ |
| 426 | { GPIO_LP_GPP_F21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 427 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 428 | /* EMMC_CLK */ |
| 429 | { GPIO_LP_GPP_F22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 430 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 431 | /* USIM_DET */ |
| 432 | { GPIO_LP_GPP_F23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, |
| 433 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 434 | //Primary Well Group G |
| 435 | /* SD_CMD */ |
| 436 | { GPIO_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 437 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 438 | /* SD_D_0 */ |
| 439 | { GPIO_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 440 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 441 | /* SD_D_1 */ |
| 442 | { GPIO_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 443 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 444 | /* SD_D_2 */ |
| 445 | { GPIO_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 446 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 447 | /* SD_D_3 */ |
| 448 | { GPIO_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, |
| 449 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 450 | /* SD_CD */ |
| 451 | { GPIO_LP_GPP_G5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 452 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 453 | /* SD_CLK */ |
| 454 | { GPIO_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 455 | GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 456 | /* SD_WP */ |
| 457 | { GPIO_LP_GPP_G7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 458 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 459 | |
| 460 | //Deep Sleep Well Group |
| 461 | /* PCH_BATLOW */ |
| 462 | { GPIO_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 463 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 464 | /* EC_PCH_ACPRESENT */ |
| 465 | { GPIO_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 466 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 467 | /* EC_PCH_WAKE */ |
| 468 | { GPIO_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 469 | GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, |
| 470 | /* EC_PCH_PWRBTN */ |
| 471 | { GPIO_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, |
| 472 | GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, |
| 473 | /* PM_SLP_S3 */ |
| 474 | { GPIO_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 475 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 476 | /* PM_SLP_S4 */ |
| 477 | { GPIO_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 478 | GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 479 | /* PCH_SLP_SA */ |
| 480 | { GPIO_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 481 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 482 | /* USB_WAKEOUT_INTRUDET */ |
| 483 | { GPIO_LP_GPD7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 484 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 485 | /* PM_SUSCLK */ |
| 486 | { GPIO_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutLow, |
| 487 | GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 488 | /* PCH_SLP_WLAN */ |
| 489 | { GPIO_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 490 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 491 | /* PCH_SLP_S5 */ |
| 492 | { GPIO_LP_GPD10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 493 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 494 | /* PM_LANPHY_ENABLE */ |
| 495 | { GPIO_LP_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, |
| 496 | GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, |
| 497 | { END_OF_GPIO_TABLE, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, |
| 498 | GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone} }, |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 499 | }; |
| 500 | #endif |