Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 2 | |
Pratik Prajapati | 7384145 | 2017-08-28 15:11:49 -0700 | [diff] [blame] | 3 | #include <cpu/cpu.h> |
| 4 | #include <console/console.h> |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 5 | #include <device/device.h> |
Werner Zeh | cfa435a | 2018-12-14 15:14:10 +0100 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Pratik Prajapati | 7384145 | 2017-08-28 15:11:49 -0700 | [diff] [blame] | 7 | #include <fsp/util.h> |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 8 | #include <intelblocks/systemagent.h> |
| 9 | #include <soc/iomap.h> |
| 10 | #include <soc/systemagent.h> |
| 11 | |
| 12 | /* |
| 13 | * SoC implementation |
| 14 | * |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 15 | * Add all known fixed memory ranges for Host Controller/Memory |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 16 | * controller. |
| 17 | */ |
| 18 | void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
| 19 | { |
| 20 | static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 21 | { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 22 | "PCIEXBAR" }, |
| 23 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 24 | }; |
| 25 | |
| 26 | sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| 27 | ARRAY_SIZE(soc_fixed_resources)); |
Werner Zeh | cfa435a | 2018-12-14 15:14:10 +0100 | [diff] [blame] | 28 | |
| 29 | /* Add VTd resources if VTd is enabled. These resources were |
| 30 | set up by the FSP-S call. */ |
| 31 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) |
| 32 | return; |
| 33 | |
| 34 | if (MCHBAR32(GFXVTBAR) & VTBAR_ENABLED) { |
Arthur Heymans | 899acf1 | 2023-07-05 11:45:54 +0200 | [diff] [blame] | 35 | mmio_range(dev, *index, MCHBAR64(GFXVTBAR) & VTBAR_MASK, VTBAR_SIZE); |
Werner Zeh | cfa435a | 2018-12-14 15:14:10 +0100 | [diff] [blame] | 36 | (*index)++; |
| 37 | } |
| 38 | if (MCHBAR32(DEFVTBAR) & VTBAR_ENABLED) { |
Arthur Heymans | 899acf1 | 2023-07-05 11:45:54 +0200 | [diff] [blame] | 39 | mmio_range(dev, *index, MCHBAR64(DEFVTBAR) & VTBAR_MASK, VTBAR_SIZE); |
Werner Zeh | cfa435a | 2018-12-14 15:14:10 +0100 | [diff] [blame] | 40 | (*index)++; |
| 41 | } |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 42 | } |
Pratik Prajapati | 7384145 | 2017-08-28 15:11:49 -0700 | [diff] [blame] | 43 | |
| 44 | int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, |
| 45 | uint64_t *prmrr_mask) |
| 46 | { |
| 47 | const void *hob; |
| 48 | size_t hob_size, prmrr_size; |
| 49 | uint64_t phys_address_mask; |
| 50 | const uint8_t prmrr_phys_base_guid[16] = { |
| 51 | 0x38, 0x3a, 0x81, 0x9f, 0xb0, 0x6f, 0xa7, 0x4f, |
| 52 | 0xaf, 0x79, 0x8a, 0x4e, 0x74, 0xdd, 0x48, 0x33 |
| 53 | }; |
| 54 | const uint8_t prmrr_size_guid[16] = { |
| 55 | 0x44, 0xed, 0x0b, 0x99, 0x4e, 0x9b, 0x26, 0x42, |
| 56 | 0xa5, 0x97, 0x28, 0x36, 0x76, 0x6b, 0x5c, 0x41 |
| 57 | }; |
| 58 | |
| 59 | hob = fsp_find_extension_hob_by_guid(prmrr_phys_base_guid, |
| 60 | &hob_size); |
| 61 | if (!hob) { |
| 62 | printk(BIOS_ERR, "Failed to locate PRMRR base hob\n"); |
| 63 | return -1; |
| 64 | } |
| 65 | if (hob_size != sizeof(uint64_t)) { |
| 66 | printk(BIOS_ERR, "Incorrect PRMRR base hob size\n"); |
| 67 | return -1; |
| 68 | } |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 69 | *prmrr_base = *(uint64_t *)hob; |
Pratik Prajapati | 7384145 | 2017-08-28 15:11:49 -0700 | [diff] [blame] | 70 | |
| 71 | hob = fsp_find_extension_hob_by_guid(prmrr_size_guid, |
| 72 | &hob_size); |
| 73 | if (!hob) { |
| 74 | printk(BIOS_ERR, "Failed to locate PRMRR size hob\n"); |
| 75 | return -1; |
| 76 | } |
| 77 | if (hob_size != sizeof(uint64_t)) { |
| 78 | printk(BIOS_ERR, "Incorrect PRMRR base hob size\n"); |
| 79 | return -1; |
| 80 | } |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 81 | prmrr_size = *(uint64_t *)hob; |
Pratik Prajapati | 7384145 | 2017-08-28 15:11:49 -0700 | [diff] [blame] | 82 | phys_address_mask = (1ULL << cpu_phys_address_size()) - 1; |
| 83 | *prmrr_mask = phys_address_mask & ~(uint64_t)(prmrr_size - 1); |
| 84 | |
| 85 | return 0; |
| 86 | } |
Patrick Rudolph | bf72dcb | 2020-05-12 16:04:47 +0200 | [diff] [blame] | 87 | |
| 88 | uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) |
| 89 | { |
| 90 | /* Max 4GiB per rank, 2 ranks per channel. Intel Document: 332092-002 */ |
| 91 | return 8192; |
| 92 | } |