blob: 22d801e018266598163a1813bbbf0d2c6d0b5bb4 [file] [log] [blame]
Subrata Banik208587e2017-05-19 18:38:24 +05301/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Intel Corp.
5 * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
6 * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <device/device.h>
20#include <intelblocks/systemagent.h>
21#include <soc/iomap.h>
22#include <soc/systemagent.h>
23
24/*
25 * SoC implementation
26 *
27 * Add all known fixed memory ranges for Host Controller/Mmeory
28 * controller.
29 */
30void soc_add_fixed_mmio_resources(struct device *dev, int *index)
31{
32 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
33 { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
34 "PCIEXBAR" },
35 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
36 };
37
38 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
39 ARRAY_SIZE(soc_fixed_resources));
40}