Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 3 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 5 | #include <arch/symbols.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 6 | #include <assert.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 7 | #include <cf9_reset.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 8 | #include <console/console.h> |
Felix Singer | 6c3a89c | 2020-07-26 09:26:52 +0200 | [diff] [blame] | 9 | #include <device/device.h> |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 10 | #include <delay.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 11 | #include <device/pci_def.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 12 | #include <device/resource.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 13 | #include <fsp/api.h> |
| 14 | #include <fsp/util.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 15 | #include <intelblocks/cpulib.h> |
Sean Rhodes | be8cd6b | 2022-06-01 11:32:05 +0100 | [diff] [blame] | 16 | #include <intelblocks/cse.h> |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 17 | #include <intelblocks/lpc_lib.h> |
| 18 | #include <intelblocks/msr.h> |
| 19 | #include <intelblocks/pmclib.h> |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 20 | #include <intelblocks/systemagent.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 21 | #include <mrc_cache.h> |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 22 | #include <soc/cpu.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 23 | #include <soc/iomap.h> |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 24 | #include <soc/meminit.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 25 | #include <soc/pci_devs.h> |
| 26 | #include <soc/pm.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 27 | #include <soc/romstage.h> |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 28 | #include <soc/systemagent.h> |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 29 | #include <spi_flash.h> |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 30 | #include <timer.h> |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 31 | #include "chip.h" |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 32 | |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 33 | static const uint8_t hob_variable_guid[16] = { |
| 34 | 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41, |
| 35 | 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, |
| 36 | }; |
| 37 | |
Arthur Heymans | 6d6945b | 2018-12-29 14:00:46 +0100 | [diff] [blame] | 38 | static uint32_t fsp_version; |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 39 | |
Furquan Shaikh | c681409 | 2016-05-04 16:03:36 -0700 | [diff] [blame] | 40 | /* High Performance Event Timer Configuration */ |
| 41 | #define P2SB_HPTC 0x60 |
| 42 | #define P2SB_HPTC_ADDRESS_ENABLE (1 << 7) |
| 43 | /* |
| 44 | * ADDRESS_SELECT ENCODING_RANGE |
| 45 | * 0 0xFED0 0000 - 0xFED0 03FF |
| 46 | * 1 0xFED0 1000 - 0xFED0 13FF |
| 47 | * 2 0xFED0 2000 - 0xFED0 23FF |
| 48 | * 3 0xFED0 3000 - 0xFED0 33FF |
| 49 | */ |
| 50 | #define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0) |
| 51 | #define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0) |
| 52 | #define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0) |
| 53 | #define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0) |
| 54 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 55 | /* |
| 56 | * Enables several BARs and devices which are needed for memory init |
| 57 | * - MCH_BASE_ADDR is needed in order to talk to the memory controller |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 58 | * - HPET is enabled because FSP wants to store a pointer to global data in the |
| 59 | * HPET comparator register |
| 60 | */ |
| 61 | static void soc_early_romstage_init(void) |
| 62 | { |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 63 | static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { |
| 64 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 65 | }; |
| 66 | |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 67 | /* Set Fixed MMIO address into PCI configuration space */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 68 | sa_set_pci_bar(soc_fixed_pci_resources, |
| 69 | ARRAY_SIZE(soc_fixed_pci_resources)); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 70 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 71 | /* Enable decoding for HPET. Needed for FSP global pointer storage */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 72 | pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | |
Furquan Shaikh | c681409 | 2016-05-04 16:03:36 -0700 | [diff] [blame] | 73 | P2SB_HPTC_ADDRESS_ENABLE); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 74 | } |
| 75 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 76 | /* |
| 77 | * Punit Initialization code. This all isn't documented, but |
| 78 | * this is the recipe. |
| 79 | */ |
| 80 | static bool punit_init(void) |
| 81 | { |
| 82 | uint32_t reg; |
| 83 | uint32_t data; |
| 84 | struct stopwatch sw; |
| 85 | |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 86 | /* Thermal throttle activation offset */ |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 87 | configure_tcc_thermal_target(); |
John Su | 85376bf | 2018-11-06 10:51:43 +0800 | [diff] [blame] | 88 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 89 | /* |
| 90 | * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). |
| 91 | * Enable all cores here. |
| 92 | */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 93 | MCHBAR32(CORE_DISABLE_MASK) = 0x0; |
Subrata Banik | d18b53f | 2017-05-19 13:44:14 +0530 | [diff] [blame] | 94 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 95 | /* P-Unit bring up */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 96 | reg = MCHBAR32(BIOS_RESET_CPL); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 97 | if (reg == 0xffffffff) { |
| 98 | /* P-unit not found */ |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 99 | printk(BIOS_DEBUG, "Punit MMIO not available\n"); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 100 | return false; |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 101 | } |
| 102 | /* Set Punit interrupt pin IPIN offset 3D */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 103 | pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 104 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 105 | /* Set PUINT IRQ to 24 and INTPIN LOCK */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 106 | MCHBAR32(PUNIT_THERMAL_DEVICE_IRQ) = |
| 107 | PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | |
| 108 | PUINT_THERMAL_DEVICE_IRQ_LOCK; |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 109 | |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 110 | if (!CONFIG(SOC_INTEL_GEMINILAKE)) { |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 111 | data = MCHBAR32(0x7818); |
| 112 | data &= 0xFFFFE01F; |
| 113 | data |= 0x20 | 0x200; |
| 114 | MCHBAR32(0x7818) = data; |
| 115 | } |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 116 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 117 | /* Stage0 BIOS Reset Complete (RST_CPL) */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 118 | enable_bios_reset_cpl(); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 119 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 120 | /* |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 121 | * Poll for bit 8 to check if PCODE has completed its action |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 122 | * in response to BIOS Reset complete. |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 123 | * We wait here till 1 ms for the bit to get set. |
| 124 | */ |
| 125 | stopwatch_init_msecs_expire(&sw, 1); |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 126 | while (!(MCHBAR32(BIOS_RESET_CPL) & PCODE_INIT_DONE)) { |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 127 | if (stopwatch_expired(&sw)) { |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 128 | printk(BIOS_DEBUG, "PCODE Init Done Failure\n"); |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 129 | return false; |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 130 | } |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 131 | udelay(100); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 132 | } |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 133 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 134 | return true; |
| 135 | } |
| 136 | |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 137 | void set_max_freq(void) |
| 138 | { |
| 139 | if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) { |
| 140 | /* Burst Mode has been factory configured as disabled |
| 141 | * and is not available in this physical processor |
| 142 | * package. |
| 143 | */ |
| 144 | printk(BIOS_DEBUG, "Burst Mode is factory disabled\n"); |
| 145 | return; |
| 146 | } |
| 147 | |
| 148 | /* Enable burst mode */ |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 149 | cpu_burst_mode(true); |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 150 | |
| 151 | /* Enable speed step. */ |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 152 | cpu_set_eist(true); |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 153 | |
| 154 | /* Set P-State ratio */ |
| 155 | cpu_set_p_state_to_turbo_ratio(); |
| 156 | } |
| 157 | |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 158 | void mainboard_romstage_entry(void) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 159 | { |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 160 | bool s3wake; |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 161 | size_t var_size; |
Patrick Georgi | c6202e8 | 2017-10-25 18:47:27 -0400 | [diff] [blame] | 162 | struct chipset_power_state *ps = pmc_get_power_state(); |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 163 | const void *new_var_data; |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 164 | |
Kyösti Mälkki | b7908d2 | 2019-08-18 06:01:41 +0300 | [diff] [blame] | 165 | soc_early_romstage_init(); |
Usha P | aaf28d2 | 2020-02-17 15:14:18 +0530 | [diff] [blame] | 166 | report_platform_info(); |
Kyösti Mälkki | b7908d2 | 2019-08-18 06:01:41 +0300 | [diff] [blame] | 167 | |
Sean Rhodes | be8cd6b | 2022-06-01 11:32:05 +0100 | [diff] [blame] | 168 | /* Initialize Heci interfaces */ |
| 169 | heci_init(); |
| 170 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 171 | s3wake = pmc_fill_power_state(ps) == ACPI_S3; |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 172 | fsp_memory_init(s3wake); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 173 | |
| 174 | if (punit_init()) |
| 175 | set_max_freq(); |
| 176 | else |
| 177 | printk(BIOS_DEBUG, "Punit failed to initialize properly\n"); |
| 178 | |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 179 | /* Stash variable MRC data and let cache system update it later */ |
| 180 | new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid, |
| 181 | &var_size); |
| 182 | if (new_var_data) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 183 | mrc_cache_stash_data(MRC_VARIABLE_DATA, |
Arthur Heymans | 6d6945b | 2018-12-29 14:00:46 +0100 | [diff] [blame] | 184 | fsp_version, new_var_data, |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 185 | var_size); |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 186 | else |
| 187 | printk(BIOS_ERR, "Failed to determine variable data\n"); |
| 188 | |
Ravi Sarawadi | 15f6f3a | 2016-08-18 13:31:29 -0700 | [diff] [blame] | 189 | mainboard_save_dimm_info(); |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 190 | } |
| 191 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 192 | static void fill_console_params(FSPM_UPD *mupd) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 193 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 194 | if (CONFIG(CONSOLE_SERIAL)) { |
| 195 | if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) { |
Mario Scheithauer | 9e9cf27 | 2017-05-15 17:24:56 +0200 | [diff] [blame] | 196 | mupd->FspmConfig.SerialDebugPortDevice = |
| 197 | CONFIG_UART_FOR_CONSOLE; |
| 198 | /* use MMIO port type */ |
| 199 | mupd->FspmConfig.SerialDebugPortType = 2; |
| 200 | /* use 4 byte register stride */ |
| 201 | mupd->FspmConfig.SerialDebugPortStrideSize = 2; |
| 202 | /* used only for port type set to external */ |
| 203 | mupd->FspmConfig.SerialDebugPortAddress = 0; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 204 | } else if (CONFIG(DRIVERS_UART_8250IO)) { |
Mario Scheithauer | 9e9cf27 | 2017-05-15 17:24:56 +0200 | [diff] [blame] | 205 | /* use external UART for debug */ |
| 206 | mupd->FspmConfig.SerialDebugPortDevice = 3; |
| 207 | /* use I/O port type */ |
| 208 | mupd->FspmConfig.SerialDebugPortType = 1; |
| 209 | /* use 1 byte register stride */ |
| 210 | mupd->FspmConfig.SerialDebugPortStrideSize = 0; |
| 211 | /* used only for port type set to external */ |
| 212 | mupd->FspmConfig.SerialDebugPortAddress = |
| 213 | CONFIG_TTYS0_BASE; |
| 214 | } |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 215 | } else { |
| 216 | mupd->FspmConfig.SerialDebugPortType = 0; |
| 217 | } |
| 218 | } |
| 219 | |
Aaron Durbin | 9c86aafe | 2017-04-26 15:02:51 -0500 | [diff] [blame] | 220 | static void check_full_retrain(const FSPM_UPD *mupd) |
| 221 | { |
| 222 | struct chipset_power_state *ps; |
| 223 | |
| 224 | if (mupd->FspmArchUpd.BootMode != FSP_BOOT_WITH_FULL_CONFIGURATION) |
| 225 | return; |
| 226 | |
Patrick Georgi | c6202e8 | 2017-10-25 18:47:27 -0400 | [diff] [blame] | 227 | ps = pmc_get_power_state(); |
Aaron Durbin | 9c86aafe | 2017-04-26 15:02:51 -0500 | [diff] [blame] | 228 | |
| 229 | if (ps->gen_pmcon1 & WARM_RESET_STS) { |
| 230 | printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n"); |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 231 | full_reset(); |
Aaron Durbin | 9c86aafe | 2017-04-26 15:02:51 -0500 | [diff] [blame] | 232 | } |
| 233 | } |
| 234 | |
Maxim Polyakov | 1a4496e | 2020-06-20 17:26:21 +0300 | [diff] [blame] | 235 | static void soc_gpu_init_params(FSPM_UPD *mupd) |
| 236 | { |
| 237 | enum { |
Werner Zeh | f223442 | 2022-03-17 08:37:34 +0100 | [diff] [blame] | 238 | GPU_PRIMARY_IGD = 0, |
| 239 | GPU_PRIMARY_PCI = 1, |
Maxim Polyakov | 1a4496e | 2020-06-20 17:26:21 +0300 | [diff] [blame] | 240 | }; |
| 241 | /* Select primary GPU device */ |
| 242 | if (CONFIG(ONBOARD_VGA_IS_PRIMARY) && is_devfn_enabled(SA_DEVFN_IGD)) |
| 243 | mupd->FspmConfig.PrimaryVideoAdaptor = GPU_PRIMARY_IGD; |
| 244 | else |
| 245 | mupd->FspmConfig.PrimaryVideoAdaptor = GPU_PRIMARY_PCI; |
| 246 | } |
| 247 | |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 248 | static void soc_memory_init_params(FSPM_UPD *mupd) |
| 249 | { |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 250 | #if CONFIG(SOC_INTEL_GEMINILAKE) |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 251 | /* Only for GLK */ |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 252 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 253 | |
Michael Niewöhner | 490546f | 2020-09-15 12:20:08 +0200 | [diff] [blame] | 254 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
Shamile Khan | 3d9462a | 2018-03-21 14:43:42 -0700 | [diff] [blame] | 255 | |
Srinidhi N Kaushik | 5af546c | 2018-05-14 23:33:55 -0700 | [diff] [blame] | 256 | /* |
| 257 | * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. |
| 258 | * With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page |
| 259 | * table entry for this range which caused a page fault. Since this |
| 260 | * test is anyway not exhaustive, skipping the memory test in FSP. |
Shamile Khan | 3d9462a | 2018-03-21 14:43:42 -0700 | [diff] [blame] | 261 | */ |
Srinidhi N Kaushik | 5af546c | 2018-05-14 23:33:55 -0700 | [diff] [blame] | 262 | m_cfg->SkipMemoryTestUpd = 1; |
| 263 | |
| 264 | /* |
| 265 | * PCIe power sequence can be done from within FSP when provided |
| 266 | * with the GPIOs used for PERST to FSP. Since this is done in |
| 267 | * coreboot, skipping the PCIe power sequence done by FSP. |
| 268 | */ |
| 269 | m_cfg->SkipPciePowerSequence = 1; |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 270 | #endif |
| 271 | } |
| 272 | |
Shaunak Saha | 6681cf0 | 2018-03-22 06:29:57 -0700 | [diff] [blame] | 273 | static void parse_devicetree_setting(FSPM_UPD *m_upd) |
| 274 | { |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 275 | #if CONFIG(SOC_INTEL_GEMINILAKE) |
Subrata Banik | 54a3417 | 2021-06-09 03:54:58 +0530 | [diff] [blame] | 276 | m_upd->FspmConfig.TraceHubEn = is_devfn_enabled(PCH_DEVFN_NPK); |
Maxim Polyakov | 7b98e3e | 2020-02-16 11:51:57 +0300 | [diff] [blame] | 277 | #else |
Subrata Banik | 54a3417 | 2021-06-09 03:54:58 +0530 | [diff] [blame] | 278 | m_upd->FspmConfig.NpkEn = is_devfn_enabled(PCH_DEVFN_NPK); |
Shaunak Saha | 6681cf0 | 2018-03-22 06:29:57 -0700 | [diff] [blame] | 279 | #endif |
| 280 | } |
| 281 | |
Andrey Petrov | f796c6e | 2016-11-18 14:57:51 -0800 | [diff] [blame] | 282 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 283 | { |
Aaron Durbin | 9c86aafe | 2017-04-26 15:02:51 -0500 | [diff] [blame] | 284 | check_full_retrain(mupd); |
| 285 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 286 | fill_console_params(mupd); |
Maxim Polyakov | 1a4496e | 2020-06-20 17:26:21 +0300 | [diff] [blame] | 287 | soc_gpu_init_params(mupd); |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 288 | |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 289 | if (CONFIG(SOC_INTEL_GEMINILAKE)) |
Pratik Prajapati | 4bc6edf | 2017-08-29 14:11:16 -0700 | [diff] [blame] | 290 | soc_memory_init_params(mupd); |
| 291 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 292 | mainboard_memory_init_params(mupd); |
| 293 | |
Shaunak Saha | 6681cf0 | 2018-03-22 06:29:57 -0700 | [diff] [blame] | 294 | parse_devicetree_setting(mupd); |
| 295 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 296 | /* Do NOT let FSP do any GPIO pad configuration */ |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 297 | mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t)NULL; |
Andrey Petrov | 24a594f | 2016-06-28 17:37:09 -0700 | [diff] [blame] | 298 | |
Sean Rhodes | fafcb74 | 2022-01-20 21:28:31 +0000 | [diff] [blame] | 299 | mupd->FspmConfig.SkipCseRbp = CONFIG(SKIP_CSE_RBP); |
Andrey Petrov | 0910f4e | 2016-10-03 16:05:20 -0700 | [diff] [blame] | 300 | |
| 301 | /* |
| 302 | * Converged Security Engine (CSE) has secure storage functionality. |
| 303 | * HECI2 device can be used to access that functionality. However, part |
| 304 | * of S3 resume flow involves resetting HECI2 which takes 136ms. Since |
| 305 | * coreboot does not use secure storage functionality, instruct FSP to |
| 306 | * skip HECI2 reset. |
| 307 | */ |
| 308 | mupd->FspmConfig.EnableS3Heci2 = 0; |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 309 | |
| 310 | /* |
| 311 | * Apollolake splits MRC cache into two parts: constant and variable. |
| 312 | * The constant part is not expected to change often and variable is. |
| 313 | * Currently variable part consists of parameters that change on cold |
| 314 | * boots such as scrambler seed and some memory controller registers. |
| 315 | * Scrambler seed is vital for S3 resume case because attempt to use |
| 316 | * wrong/missing key renders DRAM contents useless. |
| 317 | */ |
| 318 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 319 | mupd->FspmConfig.VariableNvsBufferPtr = |
| 320 | mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version, |
| 321 | NULL); |
| 322 | |
| 323 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 324 | |
Arthur Heymans | 6d6945b | 2018-12-29 14:00:46 +0100 | [diff] [blame] | 325 | fsp_version = version; |
Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 326 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 327 | } |
| 328 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 329 | __weak |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 330 | void mainboard_memory_init_params(FSPM_UPD *mupd) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 331 | { |
| 332 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 333 | } |
Furquan Shaikh | bae6383 | 2016-06-17 15:50:24 -0700 | [diff] [blame] | 334 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 335 | __weak |
Ravi Sarawadi | 15f6f3a | 2016-08-18 13:31:29 -0700 | [diff] [blame] | 336 | void mainboard_save_dimm_info(void) |
| 337 | { |
| 338 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 339 | } |