Felix Held | dd73714 | 2021-03-26 00:44:35 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/apob_cache.h> |
| 4 | #include <commonlib/helpers.h> |
| 5 | #include <console/uart.h> |
| 6 | #include <device/device.h> |
| 7 | #include <fsp/api.h> |
Matt DeVillier | c358317 | 2022-11-11 11:48:39 -0600 | [diff] [blame] | 8 | #include <soc/platform_descriptors.h> |
Felix Held | dd73714 | 2021-03-26 00:44:35 +0100 | [diff] [blame] | 9 | #include <soc/pci_devs.h> |
| 10 | #include <soc/fsp.h> |
| 11 | #include <types.h> |
| 12 | #include "chip.h" |
| 13 | |
| 14 | void __weak mainboard_updm_update(FSP_M_CONFIG *mupd) {} |
| 15 | |
Matt DeVillier | c358317 | 2022-11-11 11:48:39 -0600 | [diff] [blame] | 16 | void __weak mb_pre_fspm(void) {} |
| 17 | |
Felix Held | dd73714 | 2021-03-26 00:44:35 +0100 | [diff] [blame] | 18 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 19 | { |
| 20 | FSP_M_CONFIG *mcfg = &mupd->FspmConfig; |
| 21 | const struct soc_amd_picasso_config *config = config_of_soc(); |
| 22 | |
| 23 | mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); |
| 24 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 25 | mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS; |
Felix Held | dd73714 | 2021-03-26 00:44:35 +0100 | [diff] [blame] | 26 | mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; |
Felix Held | dd73714 | 2021-03-26 00:44:35 +0100 | [diff] [blame] | 27 | mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); |
| 28 | mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); |
| 29 | mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; |
| 30 | mcfg->serial_port_baudrate = get_uart_baudrate(); |
| 31 | mcfg->serial_port_refclk = uart_platform_refclk(); |
| 32 | |
| 33 | mcfg->system_config = config->system_config; |
| 34 | |
| 35 | if ((config->slow_ppt_limit_mW) && |
| 36 | (config->fast_ppt_limit_mW) && |
| 37 | (config->slow_ppt_time_constant_s) && |
| 38 | (config->stapm_time_constant_s)) { |
| 39 | mcfg->slow_ppt_limit_mW = config->slow_ppt_limit_mW; |
| 40 | mcfg->fast_ppt_limit_mW = config->fast_ppt_limit_mW; |
| 41 | mcfg->slow_ppt_time_constant_s = config->slow_ppt_time_constant_s; |
| 42 | mcfg->stapm_time_constant_s = config->stapm_time_constant_s; |
| 43 | } |
| 44 | |
| 45 | mcfg->ccx_down_core_mode = config->downcore_mode; |
| 46 | mcfg->ccx_disable_smt = config->smt_disable; |
| 47 | |
| 48 | mcfg->sustained_power_limit_mW = config->sustained_power_limit_mW; |
| 49 | mcfg->prochot_l_deassertion_ramp_time_ms = config->prochot_l_deassertion_ramp_time_ms; |
| 50 | mcfg->thermctl_limit_degreeC = config->thermctl_limit_degreeC; |
| 51 | mcfg->psi0_current_limit_mA = config->psi0_current_limit_mA; |
| 52 | mcfg->psi0_soc_current_limit_mA = config->psi0_soc_current_limit_mA; |
| 53 | mcfg->vddcr_soc_voltage_margin_mV = config->vddcr_soc_voltage_margin_mV; |
| 54 | mcfg->vddcr_vdd_voltage_margin_mV = config->vddcr_vdd_voltage_margin_mV; |
| 55 | mcfg->vrm_maximum_current_limit_mA = config->vrm_maximum_current_limit_mA; |
| 56 | mcfg->vrm_soc_maximum_current_limit_mA = config->vrm_soc_maximum_current_limit_mA; |
| 57 | mcfg->vrm_current_limit_mA = config->vrm_current_limit_mA; |
| 58 | mcfg->vrm_soc_current_limit_mA = config->vrm_soc_current_limit_mA; |
| 59 | mcfg->sb_tsi_alert_comparator_mode_en = config->sb_tsi_alert_comparator_mode_en; |
| 60 | mcfg->core_dldo_bypass = config->core_dldo_bypass; |
| 61 | mcfg->min_soc_vid_offset = config->min_soc_vid_offset; |
| 62 | mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz; |
| 63 | mcfg->telemetry_vddcr_vdd_slope_mA = config->telemetry_vddcr_vdd_slope_mA; |
| 64 | mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset; |
| 65 | mcfg->telemetry_vddcr_soc_slope_mA = config->telemetry_vddcr_soc_slope_mA; |
| 66 | mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; |
Felix Held | bc0032a | 2021-09-20 15:12:56 +0200 | [diff] [blame] | 67 | mcfg->hd_audio_enable = is_dev_enabled(DEV_PTR(hda)); |
| 68 | mcfg->sata_enable = is_dev_enabled(DEV_PTR(sata)); |
Patrick Huang | ed1592b | 2021-04-20 20:40:09 +0800 | [diff] [blame] | 69 | mcfg->hdmi2_disable = config->hdmi2_disable; |
Felix Held | dd73714 | 2021-03-26 00:44:35 +0100 | [diff] [blame] | 70 | |
Felix Held | 0fec867 | 2021-05-25 21:07:23 +0200 | [diff] [blame] | 71 | /* PCIe power vs. speed */ |
| 72 | mcfg->pspp_policy = config->pspp_policy; |
| 73 | |
Felix Held | dd73714 | 2021-03-26 00:44:35 +0100 | [diff] [blame] | 74 | mainboard_updm_update(mcfg); |
Matt DeVillier | c358317 | 2022-11-11 11:48:39 -0600 | [diff] [blame] | 75 | mb_pre_fspm(); |
Felix Held | dd73714 | 2021-03-26 00:44:35 +0100 | [diff] [blame] | 76 | } |