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review.coreboot.org / coreboot / 4e9bb3308e811000eb089be6b03658e4cb9a4717 / . / src / soc / amd / picasso / fsp_m_params.c
blob: 6483394294a18c3475d2eff806af3b5637b45983 [file] [log] [blame]
Felix Helddd737142021-03-26 00:44:35 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <amdblocks/apob_cache.h>
4#include <commonlib/helpers.h>
5#include <console/uart.h>
6#include <device/device.h>
7#include <fsp/api.h>
8#include <soc/pci_devs.h>
9#include <soc/fsp.h>
10#include <types.h>
11#include "chip.h"
12
13void __weak mainboard_updm_update(FSP_M_CONFIG *mupd) {}
14
Felix Helddd737142021-03-26 00:44:35 +0100[diff] [blame]15void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
16{
17 FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
18 const struct soc_amd_picasso_config *config = config_of_soc();
19
20 mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
21
Shelley Chen4e9bb332021-10-20 15:43:45 -0700[diff] [blame^]22 mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
Felix Helddd737142021-03-26 00:44:35 +0100[diff] [blame]23 mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
Felix Helddd737142021-03-26 00:44:35 +0100[diff] [blame]24 mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
25 mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
26 mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
27 mcfg->serial_port_baudrate = get_uart_baudrate();
28 mcfg->serial_port_refclk = uart_platform_refclk();
29
30 mcfg->system_config = config->system_config;
31
32 if ((config->slow_ppt_limit_mW) &&
33 (config->fast_ppt_limit_mW) &&
34 (config->slow_ppt_time_constant_s) &&
35 (config->stapm_time_constant_s)) {
36 mcfg->slow_ppt_limit_mW = config->slow_ppt_limit_mW;
37 mcfg->fast_ppt_limit_mW = config->fast_ppt_limit_mW;
38 mcfg->slow_ppt_time_constant_s = config->slow_ppt_time_constant_s;
39 mcfg->stapm_time_constant_s = config->stapm_time_constant_s;
40 }
41
42 mcfg->ccx_down_core_mode = config->downcore_mode;
43 mcfg->ccx_disable_smt = config->smt_disable;
44
45 mcfg->sustained_power_limit_mW = config->sustained_power_limit_mW;
46 mcfg->prochot_l_deassertion_ramp_time_ms = config->prochot_l_deassertion_ramp_time_ms;
47 mcfg->thermctl_limit_degreeC = config->thermctl_limit_degreeC;
48 mcfg->psi0_current_limit_mA = config->psi0_current_limit_mA;
49 mcfg->psi0_soc_current_limit_mA = config->psi0_soc_current_limit_mA;
50 mcfg->vddcr_soc_voltage_margin_mV = config->vddcr_soc_voltage_margin_mV;
51 mcfg->vddcr_vdd_voltage_margin_mV = config->vddcr_vdd_voltage_margin_mV;
52 mcfg->vrm_maximum_current_limit_mA = config->vrm_maximum_current_limit_mA;
53 mcfg->vrm_soc_maximum_current_limit_mA = config->vrm_soc_maximum_current_limit_mA;
54 mcfg->vrm_current_limit_mA = config->vrm_current_limit_mA;
55 mcfg->vrm_soc_current_limit_mA = config->vrm_soc_current_limit_mA;
56 mcfg->sb_tsi_alert_comparator_mode_en = config->sb_tsi_alert_comparator_mode_en;
57 mcfg->core_dldo_bypass = config->core_dldo_bypass;
58 mcfg->min_soc_vid_offset = config->min_soc_vid_offset;
59 mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz;
60 mcfg->telemetry_vddcr_vdd_slope_mA = config->telemetry_vddcr_vdd_slope_mA;
61 mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset;
62 mcfg->telemetry_vddcr_soc_slope_mA = config->telemetry_vddcr_soc_slope_mA;
63 mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
Felix Heldbc0032a2021-09-20 15:12:56 +0200[diff] [blame]64 mcfg->hd_audio_enable = is_dev_enabled(DEV_PTR(hda));
65 mcfg->sata_enable = is_dev_enabled(DEV_PTR(sata));
Patrick Huanged1592b2021-04-20 20:40:09 +0800[diff] [blame]66 mcfg->hdmi2_disable = config->hdmi2_disable;
Felix Helddd737142021-03-26 00:44:35 +0100[diff] [blame]67
Felix Held0fec8672021-05-25 21:07:23 +0200[diff] [blame]68 /* PCIe power vs. speed */
69 mcfg->pspp_policy = config->pspp_policy;
70
Felix Helddd737142021-03-26 00:44:35 +0100[diff] [blame]71 mainboard_updm_update(mcfg);
72}