Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 3 | #include <console/console.h> |
Kyösti Mälkki | 7fbed22 | 2019-07-11 08:14:07 +0300 | [diff] [blame] | 4 | #include <delay.h> |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Elyes HAOUAS | 420d7e0 | 2019-04-21 18:39:34 +0200 | [diff] [blame] | 7 | #include <cf9_reset.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 9 | #include <device/device.h> |
Julius Werner | 7a8a4ab | 2015-05-22 16:26:40 -0700 | [diff] [blame] | 10 | #include <lib.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 11 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 12 | #include <spd.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 13 | #include <string.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 14 | #include "raminit.h" |
| 15 | #include "i945.h" |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 16 | #include "chip.h" |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 17 | #include <device/dram/ddr2.h> |
Patrick Georgi | 771328f | 2015-07-13 19:24:07 +0200 | [diff] [blame] | 18 | #include <timestamp.h> |
Rudolf Marek | c436953 | 2010-12-13 19:59:13 +0000 | [diff] [blame] | 19 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 20 | /* Debugging macros. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 21 | #if CONFIG(DEBUG_RAM_SETUP) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 22 | #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 23 | #else |
| 24 | #define PRINTK_DEBUG(x...) |
| 25 | #endif |
| 26 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 27 | #define RAM_INITIALIZATION_COMPLETE (1 << 19) |
| 28 | |
| 29 | #define RAM_COMMAND_SELF_REFRESH (0x0 << 16) |
| 30 | #define RAM_COMMAND_NOP (0x1 << 16) |
| 31 | #define RAM_COMMAND_PRECHARGE (0x2 << 16) |
| 32 | #define RAM_COMMAND_MRS (0x3 << 16) |
| 33 | #define RAM_COMMAND_EMRS (0x4 << 16) |
| 34 | #define RAM_COMMAND_CBR (0x6 << 16) |
| 35 | #define RAM_COMMAND_NORMAL (0x7 << 16) |
| 36 | |
| 37 | #define RAM_EMRS_1 (0x0 << 21) |
| 38 | #define RAM_EMRS_2 (0x1 << 21) |
| 39 | #define RAM_EMRS_3 (0x2 << 21) |
| 40 | |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 41 | #define DEFAULT_PCI_MMIO_SIZE 768 |
Sven Schnelle | 541269b | 2011-02-21 09:39:17 +0000 | [diff] [blame] | 42 | static int get_dimm_spd_address(struct sys_info *sysinfo, int device) |
| 43 | { |
| 44 | if (sysinfo->spd_addresses) |
| 45 | return sysinfo->spd_addresses[device]; |
| 46 | else |
| 47 | return DIMM0 + device; |
| 48 | |
| 49 | } |
| 50 | |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 51 | static __attribute__((noinline)) void do_ram_command(u32 command) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 52 | { |
| 53 | u32 reg32; |
| 54 | |
| 55 | reg32 = MCHBAR32(DCC); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 56 | reg32 &= ~((3<<21) | (1<<20) | (1<<19) | (7 << 16)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 57 | reg32 |= command; |
| 58 | |
| 59 | /* Also set Init Complete */ |
| 60 | if (command == RAM_COMMAND_NORMAL) |
| 61 | reg32 |= RAM_INITIALIZATION_COMPLETE; |
| 62 | |
| 63 | PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32); |
| 64 | |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 65 | MCHBAR32(DCC) = reg32; /* This is the actual magic */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 66 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 67 | PRINTK_DEBUG("...done\n"); |
Stefan Reinauer | d058ad1 | 2010-08-26 12:43:58 +0000 | [diff] [blame] | 68 | |
| 69 | udelay(1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 70 | } |
| 71 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 72 | static void ram_read32(u32 offset) |
| 73 | { |
Elyes HAOUAS | 15279a9 | 2016-07-28 21:05:26 +0200 | [diff] [blame] | 74 | PRINTK_DEBUG(" RAM read: %08x\n", offset); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 75 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 76 | read32((void *)offset); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Stefan Reinauer | 3c0bfaf | 2010-12-27 11:34:57 +0000 | [diff] [blame] | 79 | void sdram_dump_mchbar_registers(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 80 | { |
| 81 | int i; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 82 | printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 83 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 84 | for (i = 0; i < 0xfff; i += 4) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 85 | if (MCHBAR32(i) == 0) |
| 86 | continue; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 87 | printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 88 | } |
| 89 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 90 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 91 | static int memclk(void) |
| 92 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 93 | int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 94 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 95 | switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { |
| 96 | case 1: return 400; |
| 97 | case 2: return 533; |
| 98 | case 3: return 667; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 99 | default: |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 100 | printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 101 | ((MCHBAR32(CLKCFG) >> 4) & 7) - offset); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 102 | } |
| 103 | return -1; |
| 104 | } |
| 105 | |
Peter Stuge | 76d9143 | 2010-10-01 10:02:33 +0000 | [diff] [blame] | 106 | static u16 fsbclk(void) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 107 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 108 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 109 | switch (MCHBAR32(CLKCFG) & 7) { |
| 110 | case 0: return 400; |
| 111 | case 1: return 533; |
| 112 | case 3: return 667; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 113 | default: |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 114 | printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 115 | MCHBAR32(CLKCFG) & 7); |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 116 | } |
| 117 | return 0xffff; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 118 | } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 119 | switch (MCHBAR32(CLKCFG) & 7) { |
| 120 | case 0: return 1066; |
| 121 | case 1: return 533; |
| 122 | case 2: return 800; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 123 | default: |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 124 | printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 125 | MCHBAR32(CLKCFG) & 7); |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 126 | } |
| 127 | return 0xffff; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 128 | } |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 129 | } |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 130 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 131 | static int sdram_capabilities_max_supported_memory_frequency(void) |
| 132 | { |
| 133 | u32 reg32; |
| 134 | |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 135 | #if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY |
| 136 | return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 137 | #endif |
| 138 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 139 | reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 140 | reg32 &= (7 << 0); |
| 141 | |
| 142 | switch (reg32) { |
| 143 | case 4: return 400; |
| 144 | case 3: return 533; |
| 145 | case 2: return 667; |
| 146 | } |
| 147 | /* Newer revisions of this chipset rather support faster memory clocks, |
| 148 | * so if it's a reserved value, return the fastest memory clock that we |
| 149 | * know of and can handle |
| 150 | */ |
| 151 | return 667; |
| 152 | } |
| 153 | |
| 154 | /** |
| 155 | * @brief determine whether chipset is capable of dual channel interleaved mode |
| 156 | * |
| 157 | * @return 1 if interleaving is supported, 0 otherwise |
| 158 | */ |
| 159 | static int sdram_capabilities_interleave(void) |
| 160 | { |
| 161 | u32 reg32; |
| 162 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 163 | reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 164 | reg32 >>= 25; |
| 165 | reg32 &= 1; |
| 166 | |
| 167 | return (!reg32); |
| 168 | } |
| 169 | |
| 170 | /** |
| 171 | * @brief determine whether chipset is capable of two memory channels |
| 172 | * |
| 173 | * @return 1 if dual channel operation is supported, 0 otherwise |
| 174 | */ |
| 175 | static int sdram_capabilities_dual_channel(void) |
| 176 | { |
| 177 | u32 reg32; |
| 178 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 179 | reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 180 | reg32 >>= 24; |
| 181 | reg32 &= 1; |
| 182 | |
| 183 | return (!reg32); |
| 184 | } |
| 185 | |
| 186 | static int sdram_capabilities_enhanced_addressing_xor(void) |
| 187 | { |
| 188 | u8 reg8; |
| 189 | |
| 190 | reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ |
| 191 | reg8 &= (1 << 7); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 192 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 193 | return (!reg8); |
| 194 | } |
| 195 | |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 196 | /* TODO check if we ever need this function */ |
Stefan Reinauer | 53b0ea4 | 2010-03-22 11:50:52 +0000 | [diff] [blame] | 197 | #if 0 |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 198 | static int sdram_capabilities_MEM4G_disable(void) |
| 199 | { |
| 200 | u8 reg8; |
| 201 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 202 | reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 203 | reg8 &= (1 << 0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 204 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 205 | return (reg8 != 0); |
| 206 | } |
Stefan Reinauer | 53b0ea4 | 2010-03-22 11:50:52 +0000 | [diff] [blame] | 207 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 208 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 209 | #define GFX_FREQUENCY_CAP_166MHZ 0x04 |
| 210 | #define GFX_FREQUENCY_CAP_200MHZ 0x03 |
| 211 | #define GFX_FREQUENCY_CAP_250MHZ 0x02 |
| 212 | #define GFX_FREQUENCY_CAP_ALL 0x00 |
| 213 | |
| 214 | static int sdram_capabilities_core_frequencies(void) |
| 215 | { |
| 216 | u8 reg8; |
| 217 | |
| 218 | reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ |
| 219 | reg8 &= (1 << 3) | (1 << 2) | (1 << 1); |
| 220 | reg8 >>= 1; |
| 221 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 222 | return reg8; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 223 | } |
| 224 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 225 | static void sdram_detect_errors(struct sys_info *sysinfo) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 226 | { |
| 227 | u8 reg8; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 228 | u8 do_reset = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 229 | |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 230 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 231 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 232 | if (reg8 & ((1<<7)|(1<<2))) { |
| 233 | if (reg8 & (1<<2)) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 234 | printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); |
Stefan Reinauer | f98ad3a | 2010-03-05 18:25:19 +0000 | [diff] [blame] | 235 | /* Write back clears bit 2 */ |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 236 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); |
Stefan Reinauer | f98ad3a | 2010-03-05 18:25:19 +0000 | [diff] [blame] | 237 | do_reset = 1; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 238 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | if (reg8 & (1<<7)) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 242 | printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 243 | reg8 &= ~(1<<7); |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 244 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 245 | do_reset = 1; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 246 | } |
| 247 | |
| 248 | /* Set SLP_S3# Assertion Stretch Enable */ |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 249 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 250 | reg8 |= (1 << 3); |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 251 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 252 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 253 | if (do_reset) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 254 | printk(BIOS_DEBUG, "Reset required.\n"); |
Elyes HAOUAS | 420d7e0 | 2019-04-21 18:39:34 +0200 | [diff] [blame] | 255 | full_reset(); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 256 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | /* Set DRAM initialization bit in ICH7 */ |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 260 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 261 | reg8 |= (1<<7); |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 262 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 263 | |
Peter Stuge | 751508a | 2012-01-27 22:17:09 +0100 | [diff] [blame] | 264 | /* clear self refresh status if check is disabled or not a resume */ |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 265 | if (!CONFIG(CHECK_SLFRCS_ON_RESUME) || sysinfo->boot_path != BOOT_PATH_RESUME) { |
Patrick Georgi | 86a1110 | 2013-03-15 14:11:37 +0100 | [diff] [blame] | 266 | MCHBAR8(SLFRCS) |= 3; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 267 | } else { |
| 268 | /* Validate self refresh config */ |
| 269 | if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) || |
| 270 | (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && |
Patrick Georgi | 86a1110 | 2013-03-15 14:11:37 +0100 | [diff] [blame] | 271 | !(MCHBAR8(SLFRCS) & (1<<0))) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 272 | do_reset = 1; |
| 273 | } |
| 274 | if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) || |
| 275 | (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) && |
Patrick Georgi | 86a1110 | 2013-03-15 14:11:37 +0100 | [diff] [blame] | 276 | !(MCHBAR8(SLFRCS) & (1<<1))) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 277 | do_reset = 1; |
| 278 | } |
| 279 | } |
| 280 | |
| 281 | if (do_reset) { |
| 282 | printk(BIOS_DEBUG, "Reset required.\n"); |
Elyes HAOUAS | 420d7e0 | 2019-04-21 18:39:34 +0200 | [diff] [blame] | 283 | full_reset(); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 284 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 285 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 286 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 287 | struct timings { |
| 288 | u32 min_tCLK_cas[8]; |
| 289 | u32 min_tRAS; |
| 290 | u32 min_tRP; |
| 291 | u32 min_tRCD; |
| 292 | u32 min_tWR; |
| 293 | u32 min_tRFC; |
| 294 | u32 max_tRR; |
| 295 | u8 cas_mask; |
| 296 | }; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 297 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 298 | /** |
| 299 | * @brief loop over dimms and save maximal timings |
| 300 | */ |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 301 | static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved_timings) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 302 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 303 | |
| 304 | int i, j; |
| 305 | u8 raw_spd[SPD_SIZE_MAX_DDR2]; |
| 306 | u8 dimm_mask = 0; |
| 307 | |
| 308 | memset(saved_timings, 0, sizeof(*saved_timings)); |
| 309 | saved_timings->max_tRR = UINT32_MAX; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 310 | saved_timings->cas_mask = SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4 |
| 311 | | SPD_CAS_LATENCY_DDR2_5; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 312 | |
| 313 | /** |
| 314 | * i945 supports two DIMMs, in two configurations: |
| 315 | * |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 316 | * - single channel with two DIMMs |
| 317 | * - dual channel with one DIMM per channel |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 318 | * |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 319 | * In practice dual channel mainboards have their SPD at 0x50/0x52 |
| 320 | * whereas single channel configurations have their SPD at 0x50/0x51. |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 321 | * |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 322 | * The capability register knows a lot about the channel configuration |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 323 | * but for now we stick with the information we gather via SPD. |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 324 | */ |
| 325 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 326 | printk(BIOS_DEBUG, "This mainboard supports "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 327 | if (sdram_capabilities_dual_channel()) { |
| 328 | sysinfo->dual_channel = 1; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 329 | printk(BIOS_DEBUG, "Dual Channel Operation.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 330 | } else { |
| 331 | sysinfo->dual_channel = 0; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 332 | printk(BIOS_DEBUG, "only Single Channel Operation.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 333 | } |
| 334 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 335 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 336 | for (i = 0; i < (2 * DIMM_SOCKETS); i++) { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 337 | int device = get_dimm_spd_address(sysinfo, i), bytes_read; |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 338 | struct dimm_attr_ddr2_st dimm_info; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 339 | |
| 340 | /* Initialize the socket information with a sane value */ |
| 341 | sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; |
| 342 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 343 | /* Dual Channel not supported, but Channel 1? Bail out */ |
| 344 | if (!sdram_capabilities_dual_channel() && (i >> 1)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 345 | continue; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 346 | |
Kyösti Mälkki | bd65985 | 2020-01-05 20:00:18 +0200 | [diff] [blame] | 347 | if (smbus_read_byte(device, SPD_MEMORY_TYPE) != |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 348 | SPD_MEMORY_TYPE_SDRAM_DDR2) { |
| 349 | printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: N/A\n", |
| 350 | (i >> 1), (i & 1)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 351 | continue; |
| 352 | } |
| 353 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 354 | /* |
| 355 | * spd_decode_ddr2() needs a 128-byte sized array but |
| 356 | * only the first 64 bytes contain data needed for raminit. |
| 357 | */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 358 | |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 359 | bytes_read = i2c_eeprom_read(device, 0, 64, raw_spd); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 360 | printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n"); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 361 | if (CONFIG(DEBUG_RAM_SETUP) && bytes_read > 0) |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 362 | hexdump(raw_spd, bytes_read); |
Arthur Heymans | 5661945 | 2017-09-21 09:12:42 +0200 | [diff] [blame] | 363 | if (bytes_read != 64) { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 364 | /* Try again with SMBUS byte read */ |
| 365 | printk(BIOS_DEBUG, "i2c block operation failed," |
Paul Menzel | 105e368 | 2017-09-21 08:11:05 +0200 | [diff] [blame] | 366 | " trying smbus byte operation.\n"); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 367 | for (j = 0; j < 64; j++) |
Kyösti Mälkki | bd65985 | 2020-01-05 20:00:18 +0200 | [diff] [blame] | 368 | raw_spd[j] = smbus_read_byte(device, j); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 369 | if (CONFIG(DEBUG_RAM_SETUP)) |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 370 | hexdump(raw_spd, 64); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 371 | } |
Arthur Heymans | 5661945 | 2017-09-21 09:12:42 +0200 | [diff] [blame] | 372 | |
| 373 | if (spd_decode_ddr2(&dimm_info, raw_spd) != SPD_STATUS_OK) { |
| 374 | printk(BIOS_WARNING, "Encountered problems with SPD, " |
| 375 | "skipping this DIMM.\n"); |
| 376 | continue; |
| 377 | } |
| 378 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 379 | if (CONFIG(DEBUG_RAM_SETUP)) |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 380 | dram_print_spd_ddr2(&dimm_info); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 381 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 382 | if (dimm_info.flags.is_ecc) |
| 383 | die("\nError: ECC memory not supported by this chipset\n"); |
| 384 | |
| 385 | if (spd_dimm_is_registered_ddr2(dimm_info.dimm_type)) |
| 386 | die("\nError: Registered memory not supported by this chipset\n"); |
| 387 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 388 | printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 389 | /** |
| 390 | * There are 5 different possible populations for a DIMM socket: |
| 391 | * 0. x16 double ranked (X16DS) |
| 392 | * 1. x8 double ranked (X8DS) |
| 393 | * 2. x16 single ranked (X16SS) |
| 394 | * 3. x8 double stacked (X8DDS) |
| 395 | * 4. Unpopulated |
| 396 | */ |
| 397 | switch (dimm_info.width) { |
| 398 | case 8: |
| 399 | switch (dimm_info.ranks) { |
| 400 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 401 | printk(BIOS_DEBUG, "x8DDS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 402 | sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; |
| 403 | break; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 404 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 405 | printk(BIOS_DEBUG, "x8DS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 406 | sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; |
| 407 | break; |
| 408 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 409 | printk(BIOS_DEBUG, "Unsupported.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 410 | } |
| 411 | break; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 412 | case 16: |
| 413 | switch (dimm_info.ranks) { |
| 414 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 415 | printk(BIOS_DEBUG, "x16DS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 416 | sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; |
| 417 | break; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 418 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 419 | printk(BIOS_DEBUG, "x16SS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 420 | sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; |
| 421 | break; |
| 422 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 423 | printk(BIOS_DEBUG, "Unsupported.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 424 | } |
| 425 | break; |
| 426 | default: |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 427 | die("Unsupported DDR-II memory width.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 428 | } |
| 429 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 430 | /* Is the current DIMM a stacked DIMM? */ |
| 431 | if (dimm_info.flags.stacked) |
| 432 | sysinfo->package = SYSINFO_PACKAGE_STACKED; |
| 433 | |
| 434 | if (!dimm_info.flags.bl8) |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 435 | die("Only DDR-II RAM with burst length 8 is supported.\n"); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 436 | |
| 437 | if (dimm_info.ranksize_mb < 128) |
| 438 | die("DDR-II rank size smaller than 128MB is not supported.\n"); |
| 439 | |
| 440 | sysinfo->banksize[i * 2] = dimm_info.ranksize_mb / 32; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 441 | printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 442 | if (dimm_info.ranks == 2) { |
| 443 | sysinfo->banksize[(i * 2) + 1] = |
| 444 | dimm_info.ranksize_mb / 32; |
| 445 | printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", |
| 446 | i, sysinfo->banksize[(i * 2) + 1] * 32); |
| 447 | } |
| 448 | |
| 449 | |
| 450 | sysinfo->rows[i] = dimm_info.row_bits; |
| 451 | sysinfo->cols[i] = dimm_info.col_bits; |
| 452 | sysinfo->banks[i] = dimm_info.banks; |
| 453 | |
| 454 | /* int min_tRAS, min_tRP, min_tRCD, min_tWR, min_tRFC; */ |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 455 | saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, dimm_info.tRAS); |
| 456 | saved_timings->min_tRP = MAX(saved_timings->min_tRP, dimm_info.tRP); |
| 457 | saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, dimm_info.tRCD); |
| 458 | saved_timings->min_tWR = MAX(saved_timings->min_tWR, dimm_info.tWR); |
| 459 | saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, dimm_info.tRFC); |
| 460 | saved_timings->max_tRR = MIN(saved_timings->max_tRR, dimm_info.tRR); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 461 | saved_timings->cas_mask &= dimm_info.cas_supported; |
| 462 | for (j = 0; j < 8; j++) { |
| 463 | if (!(saved_timings->cas_mask & (1 << j))) |
| 464 | saved_timings->min_tCLK_cas[j] = 0; |
| 465 | else |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 466 | saved_timings->min_tCLK_cas[j] = MAX(dimm_info.cycle_time[j], |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 467 | saved_timings->min_tCLK_cas[j]); |
| 468 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 469 | dimm_mask |= (1 << i); |
| 470 | } |
Elyes HAOUAS | 9749a85 | 2018-05-09 19:06:46 +0200 | [diff] [blame] | 471 | if (!dimm_mask) |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 472 | die("No memory installed.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 473 | |
Elyes HAOUAS | 9749a85 | 2018-05-09 19:06:46 +0200 | [diff] [blame] | 474 | if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 475 | /* FIXME: Possibly does not boot in this case */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 476 | printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 477 | } |
| 478 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 479 | static void choose_tclk(struct sys_info *sysinfo, struct timings *saved_timings) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 480 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 481 | u32 ctrl_min_tclk; |
| 482 | int try_cas; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 483 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 484 | ctrl_min_tclk = 2 * 256 * 1000 / sdram_capabilities_max_supported_memory_frequency(); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 485 | normalize_tck(&ctrl_min_tclk); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 486 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 487 | try_cas = spd_get_msbs(saved_timings->cas_mask); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 488 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 489 | while (saved_timings->cas_mask & (1 << try_cas) && try_cas > 0) { |
| 490 | sysinfo->cas = try_cas; |
| 491 | sysinfo->tclk = saved_timings->min_tCLK_cas[try_cas]; |
| 492 | if (sysinfo->tclk >= ctrl_min_tclk && |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 493 | saved_timings->min_tCLK_cas[try_cas] != |
| 494 | saved_timings->min_tCLK_cas[try_cas - 1]) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 495 | break; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 496 | try_cas--; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 497 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 498 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 499 | normalize_tck(&sysinfo->tclk); |
| 500 | |
| 501 | if ((sysinfo->cas < 3) || (sysinfo->tclk == 0)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 502 | die("Could not find common memory frequency and CAS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 503 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 504 | /* |
| 505 | * The loop can still results in a timing too fast for the |
| 506 | * memory controller. |
| 507 | */ |
| 508 | if (sysinfo->tclk < ctrl_min_tclk) |
| 509 | sysinfo->tclk = ctrl_min_tclk; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 510 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 511 | switch (sysinfo->tclk) { |
| 512 | case TCK_200MHZ: |
| 513 | sysinfo->memory_frequency = 400; |
| 514 | break; |
| 515 | case TCK_266MHZ: |
| 516 | sysinfo->memory_frequency = 533; |
| 517 | break; |
| 518 | case TCK_333MHZ: |
| 519 | sysinfo->memory_frequency = 667; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 520 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 521 | } |
| 522 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 523 | printk(BIOS_DEBUG, |
| 524 | "Memory will be driven at %dMT with CAS=%d clocks\n", |
| 525 | sysinfo->memory_frequency, sysinfo->cas); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 526 | } |
| 527 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 528 | static void derive_timings(struct sys_info *sysinfo, struct timings *saved_timings) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 529 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 530 | sysinfo->tras = DIV_ROUND_UP(saved_timings->min_tRAS, sysinfo->tclk); |
| 531 | if (sysinfo->tras > 0x18) |
| 532 | die("DDR-II Module does not support this frequency (tRAS error)\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 533 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 534 | sysinfo->trp = DIV_ROUND_UP(saved_timings->min_tRP, sysinfo->tclk); |
| 535 | if (sysinfo->trp > 6) |
| 536 | die("DDR-II Module does not support this frequency (tRP error)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 537 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 538 | sysinfo->trcd = DIV_ROUND_UP(saved_timings->min_tRCD, sysinfo->tclk); |
| 539 | if (sysinfo->trcd > 6) |
| 540 | die("DDR-II Module does not support this frequency (tRCD error)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 541 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 542 | sysinfo->twr = DIV_ROUND_UP(saved_timings->min_tWR, sysinfo->tclk); |
| 543 | if (sysinfo->twr > 5) |
| 544 | die("DDR-II Module does not support this frequency (tWR error)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 545 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 546 | sysinfo->trfc = DIV_ROUND_UP(saved_timings->min_tRFC, sysinfo->tclk); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 547 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 548 | printk(BIOS_DEBUG, "tRAS = %d cycles\n", sysinfo->tras); |
| 549 | printk(BIOS_DEBUG, "tRP = %d cycles\n", sysinfo->trp); |
| 550 | printk(BIOS_DEBUG, "tRCD = %d cycles\n", sysinfo->trcd); |
| 551 | printk(BIOS_DEBUG, "tWR = %d cycles\n", sysinfo->twr); |
| 552 | printk(BIOS_DEBUG, "tRFC = %d cycles\n", sysinfo->trfc); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 553 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 554 | /* Refresh is slower than 15.6us, use 15.6us */ |
| 555 | /* tRR is decoded in units of 1/256us */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 556 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 557 | #define T_RR_7_8US 2000000 |
| 558 | #define T_RR_15_6US 4000000 |
| 559 | #define REFRESH_7_8US 1 |
| 560 | #define REFRESH_15_6US 0 |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 561 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 562 | if (saved_timings->max_tRR < T_RR_7_8US) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 563 | die("DDR-II module has unsupported refresh value\n"); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 564 | else if (saved_timings->max_tRR < T_RR_15_6US) |
| 565 | sysinfo->refresh = REFRESH_7_8US; |
| 566 | else |
| 567 | sysinfo->refresh = REFRESH_15_6US; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 568 | printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 569 | } |
| 570 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 571 | /** |
| 572 | * @brief Get generic DIMM parameters. |
| 573 | * @param sysinfo Central memory controller information structure |
| 574 | * |
| 575 | * This function gathers several pieces of information for each system DIMM: |
| 576 | * o DIMM width (x8 / x16) |
| 577 | * o DIMM rank (single ranked / dual ranked) |
| 578 | * |
| 579 | * Also, some non-supported scenarios are detected. |
| 580 | */ |
| 581 | |
| 582 | static void sdram_get_dram_configuration(struct sys_info *sysinfo) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 583 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 584 | struct timings saved_timings; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 585 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 586 | gather_common_timing(sysinfo, &saved_timings); |
| 587 | choose_tclk(sysinfo, &saved_timings); |
| 588 | derive_timings(sysinfo, &saved_timings); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 589 | } |
| 590 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 591 | static void sdram_program_dram_width(struct sys_info *sysinfo) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 592 | { |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 593 | u16 c0dramw = 0, c1dramw = 0; |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 594 | int i, idx; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 595 | |
| 596 | if (sysinfo->dual_channel) |
| 597 | idx = 2; |
| 598 | else |
| 599 | idx = 1; |
| 600 | |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 601 | for (i = 0; i < DIMM_SOCKETS; i++) { /* Channel 0 */ |
| 602 | switch (sysinfo->dimm[i]) { |
| 603 | case SYSINFO_DIMM_X16DS: |
| 604 | c0dramw |= (0x0000) << 4*(i % 2); |
| 605 | break; |
| 606 | case SYSINFO_DIMM_X8DS: |
| 607 | c0dramw |= (0x0001) << 4*(i % 2); |
| 608 | break; |
| 609 | case SYSINFO_DIMM_X16SS: |
| 610 | c0dramw |= (0x0000) << 4*(i % 2); |
| 611 | break; |
| 612 | case SYSINFO_DIMM_X8DDS: |
| 613 | c0dramw |= (0x0005) << 4*(i % 2); |
| 614 | break; |
| 615 | case SYSINFO_DIMM_NOT_POPULATED: |
| 616 | c0dramw |= (0x0000) << 4*(i % 2); |
| 617 | break; |
| 618 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 619 | } |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 620 | for (i = DIMM_SOCKETS; i < idx * DIMM_SOCKETS; i++) { /* Channel 1 */ |
| 621 | switch (sysinfo->dimm[i]) { |
| 622 | case SYSINFO_DIMM_X16DS: |
| 623 | c1dramw |= (0x0000) << 4*(i % 2); |
| 624 | break; |
| 625 | case SYSINFO_DIMM_X8DS: |
Patrick Georgi | 68aed91 | 2018-11-16 18:00:12 +0100 | [diff] [blame] | 626 | c1dramw |= (0x0010) << 4*(i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 627 | break; |
| 628 | case SYSINFO_DIMM_X16SS: |
| 629 | c1dramw |= (0x0000) << 4*(i % 2); |
| 630 | break; |
| 631 | case SYSINFO_DIMM_X8DDS: |
Patrick Georgi | 68aed91 | 2018-11-16 18:00:12 +0100 | [diff] [blame] | 632 | c1dramw |= (0x0050) << 4*(i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 633 | break; |
| 634 | case SYSINFO_DIMM_NOT_POPULATED: |
| 635 | c1dramw |= (0x0000) << 4*(i % 2); |
| 636 | break; |
| 637 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 638 | } |
| 639 | |
| 640 | MCHBAR16(C0DRAMW) = c0dramw; |
| 641 | MCHBAR16(C1DRAMW) = c1dramw; |
| 642 | } |
| 643 | |
| 644 | static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table) |
| 645 | { |
| 646 | int i; |
| 647 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 648 | for (i = 0; i < 16; i++) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 649 | MCHBAR32(offset+(i*4)) = slew_rate_table[i]; |
| 650 | } |
| 651 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 652 | static const u32 dq2030[] = { |
| 653 | 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, |
| 654 | 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, |
| 655 | 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, |
| 656 | 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 |
| 657 | }; |
| 658 | |
| 659 | static const u32 dq2330[] = { |
| 660 | 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, |
| 661 | 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, |
| 662 | 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, |
| 663 | 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 |
| 664 | }; |
| 665 | |
| 666 | static const u32 cmd2710[] = { |
| 667 | 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, |
| 668 | 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, |
| 669 | 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, |
| 670 | 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f |
| 671 | }; |
| 672 | |
| 673 | static const u32 cmd3210[] = { |
| 674 | 0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f, |
| 675 | 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, |
| 676 | 0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f, |
| 677 | 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f |
| 678 | }; |
| 679 | |
| 680 | static const u32 clk2030[] = { |
| 681 | 0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211, |
| 682 | 0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c, |
| 683 | 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120, |
| 684 | 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937 |
| 685 | }; |
| 686 | |
| 687 | static const u32 ctl3215[] = { |
| 688 | 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908, |
| 689 | 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19, |
| 690 | 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b, |
| 691 | 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d |
| 692 | }; |
| 693 | |
| 694 | static const u32 ctl3220[] = { |
| 695 | 0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411, |
| 696 | 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e, |
| 697 | 0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311, |
| 698 | 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e |
| 699 | }; |
| 700 | |
| 701 | static const u32 nc[] = { |
| 702 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 703 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 704 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 705 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 |
| 706 | }; |
| 707 | |
| 708 | enum { |
| 709 | DQ2030, |
| 710 | DQ2330, |
| 711 | CMD2710, |
| 712 | CMD3210, |
| 713 | CLK2030, |
| 714 | CTL3215, |
| 715 | CTL3220, |
| 716 | NC, |
| 717 | }; |
| 718 | |
| 719 | static const u8 dual_channel_slew_group_lookup[] = { |
| 720 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 721 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 722 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 723 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710, |
| 724 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, |
| 725 | |
| 726 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 727 | DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, |
| 728 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 729 | DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, |
| 730 | DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, |
| 731 | |
| 732 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 733 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 734 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 735 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710, |
| 736 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, |
| 737 | |
| 738 | DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 739 | DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, |
| 740 | DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 741 | DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, |
| 742 | DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, NC, NC, |
| 743 | |
| 744 | NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 745 | NC, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, |
| 746 | NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 747 | NC, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD2710 |
| 748 | }; |
| 749 | |
| 750 | static const u8 single_channel_slew_group_lookup[] = { |
| 751 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 752 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 753 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, |
| 754 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 755 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, |
| 756 | |
| 757 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 758 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, |
| 759 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 760 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, |
| 761 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, |
| 762 | |
| 763 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, |
| 764 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 765 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, |
| 766 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 767 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, |
| 768 | |
| 769 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 770 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, |
| 771 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 772 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, |
| 773 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, |
| 774 | |
| 775 | DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 776 | DQ2330, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, |
| 777 | DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 778 | DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210 |
| 779 | }; |
| 780 | |
| 781 | static const u32 *slew_group_lookup(int dual_channel, int index) |
| 782 | { |
| 783 | const u8 *slew_group; |
| 784 | /* Dual Channel needs different tables. */ |
| 785 | if (dual_channel) |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 786 | slew_group = dual_channel_slew_group_lookup; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 787 | else |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 788 | slew_group = single_channel_slew_group_lookup; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 789 | |
| 790 | switch (slew_group[index]) { |
| 791 | case DQ2030: return dq2030; |
| 792 | case DQ2330: return dq2330; |
| 793 | case CMD2710: return cmd2710; |
| 794 | case CMD3210: return cmd3210; |
| 795 | case CLK2030: return clk2030; |
| 796 | case CTL3215: return ctl3215; |
| 797 | case CTL3220: return ctl3220; |
| 798 | case NC: return nc; |
| 799 | } |
| 800 | |
| 801 | return nc; |
| 802 | } |
| 803 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 804 | #if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 805 | /* Strength multiplier tables */ |
| 806 | static const u8 dual_channel_strength_multiplier[] = { |
| 807 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 808 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 809 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 810 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, |
| 811 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, |
| 812 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 813 | 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, |
| 814 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 815 | 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, |
| 816 | 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, |
| 817 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 818 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 819 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 820 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, |
| 821 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, |
| 822 | 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 823 | 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, |
| 824 | 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 825 | 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, |
| 826 | 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, |
| 827 | 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 828 | 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, |
| 829 | 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 830 | 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22 |
| 831 | }; |
| 832 | |
| 833 | static const u8 single_channel_strength_multiplier[] = { |
| 834 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 835 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 836 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 837 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 838 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, |
| 839 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 840 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 841 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 842 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 843 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, |
| 844 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 845 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 846 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 847 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 848 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, |
| 849 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 850 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 851 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 852 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 853 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, |
| 854 | 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 855 | 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 856 | 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 857 | 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 |
| 858 | }; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 859 | #elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 860 | static const u8 dual_channel_strength_multiplier[] = { |
| 861 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 862 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 863 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 864 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, |
| 865 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 866 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 867 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 868 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 869 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, |
| 870 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 871 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 872 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 873 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 874 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, |
| 875 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 876 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 877 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 878 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 879 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, |
| 880 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 881 | 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 882 | 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 883 | 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 884 | 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33 |
| 885 | }; |
| 886 | |
| 887 | static const u8 single_channel_strength_multiplier[] = { |
| 888 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 889 | 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 890 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 891 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 892 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 893 | 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 894 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 895 | 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 896 | 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 897 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 898 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 899 | 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 900 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 901 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 902 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 903 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 904 | 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 905 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 906 | 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 907 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 908 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 909 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 910 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 911 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00 |
| 912 | }; |
| 913 | #endif |
| 914 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 915 | static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) |
| 916 | { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 917 | const u8 *strength_multiplier; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 918 | int idx, dual_channel; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 919 | |
| 920 | /* Set Strength Multipliers */ |
| 921 | |
| 922 | /* Dual Channel needs different tables. */ |
| 923 | if (sdram_capabilities_dual_channel()) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 924 | printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 925 | strength_multiplier = dual_channel_strength_multiplier; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 926 | dual_channel = 1; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 927 | idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 928 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 929 | printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 930 | strength_multiplier = single_channel_strength_multiplier; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 931 | dual_channel = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 932 | idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1]; |
| 933 | } |
| 934 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 935 | printk(BIOS_DEBUG, "Table Index: %d\n", idx); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 936 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 937 | MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0]; |
| 938 | MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1]; |
| 939 | MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2]; |
| 940 | MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3]; |
| 941 | MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4]; |
| 942 | MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5]; |
| 943 | MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6]; |
| 944 | MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7]; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 945 | |
| 946 | /* Channel 0 */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 947 | sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0)); |
| 948 | sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1)); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 949 | if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && |
| 950 | (sysinfo->package == SYSINFO_PACKAGE_STACKED)) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 951 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 952 | sdram_write_slew_rates(G3SRPUT, ctl3220); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 953 | else |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 954 | sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2)); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 955 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 956 | sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3)); |
| 957 | sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4)); |
| 958 | sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 959 | |
| 960 | /* Channel 1 */ |
| 961 | if (sysinfo->dual_channel) { |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 962 | sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6)); |
| 963 | sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 964 | } else { |
| 965 | sdram_write_slew_rates(G7SRPUT, nc); |
| 966 | sdram_write_slew_rates(G8SRPUT, nc); |
| 967 | } |
| 968 | } |
| 969 | |
| 970 | static void sdram_enable_rcomp(void) |
| 971 | { |
| 972 | u32 reg32; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 973 | /* Enable Global Periodic RCOMP */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 974 | udelay(300); |
| 975 | reg32 = MCHBAR32(GBRCOMPCTL); |
| 976 | reg32 &= ~(1 << 23); |
| 977 | MCHBAR32(GBRCOMPCTL) = reg32; |
| 978 | } |
| 979 | |
| 980 | static void sdram_program_dll_timings(struct sys_info *sysinfo) |
| 981 | { |
Elyes HAOUAS | 44a3066 | 2017-02-23 13:14:44 +0100 | [diff] [blame] | 982 | u32 channeldll = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 983 | int i; |
| 984 | |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 985 | printk(BIOS_DEBUG, "Programming DLL Timings...\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 986 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 987 | MCHBAR16(DQSMT) &= ~((3 << 12) | (1 << 10) | (0xf << 0)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 988 | MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0); |
| 989 | |
| 990 | /* We drive both channels with the same speed */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 991 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { |
Elyes HAOUAS | 39bfc6c | 2016-10-31 10:49:33 +0100 | [diff] [blame] | 992 | switch (sysinfo->memory_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 993 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 994 | channeldll = 0x26262626; |
| 995 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 996 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 997 | channeldll = 0x22222222; |
| 998 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 999 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1000 | channeldll = 0x11111111; |
| 1001 | break; |
Elyes HAOUAS | 39bfc6c | 2016-10-31 10:49:33 +0100 | [diff] [blame] | 1002 | } |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1003 | } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Elyes HAOUAS | 39bfc6c | 2016-10-31 10:49:33 +0100 | [diff] [blame] | 1004 | switch (sysinfo->memory_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1005 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1006 | channeldll = 0x33333333; |
| 1007 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1008 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1009 | channeldll = 0x24242424; |
| 1010 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1011 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1012 | channeldll = 0x25252525; |
| 1013 | break; |
Elyes HAOUAS | 39bfc6c | 2016-10-31 10:49:33 +0100 | [diff] [blame] | 1014 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1015 | } |
| 1016 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1017 | for (i = 0; i < 4; i++) { |
Elyes HAOUAS | 44a3066 | 2017-02-23 13:14:44 +0100 | [diff] [blame] | 1018 | MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = channeldll; |
| 1019 | MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; |
| 1020 | MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; |
| 1021 | MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1022 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Elyes HAOUAS | 44a3066 | 2017-02-23 13:14:44 +0100 | [diff] [blame] | 1023 | MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; |
| 1024 | MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; |
Paul Menzel | bce7e33 | 2017-02-22 18:46:27 +0100 | [diff] [blame] | 1025 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1026 | } |
| 1027 | } |
| 1028 | |
| 1029 | static void sdram_force_rcomp(void) |
| 1030 | { |
| 1031 | u32 reg32; |
| 1032 | u8 reg8; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1033 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1034 | reg32 = MCHBAR32(ODTC); |
| 1035 | reg32 |= (1 << 28); |
| 1036 | MCHBAR32(ODTC) = reg32; |
| 1037 | |
| 1038 | reg32 = MCHBAR32(SMSRCTL); |
| 1039 | reg32 |= (1 << 0); |
| 1040 | MCHBAR32(SMSRCTL) = reg32; |
| 1041 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1042 | /* Start initial RCOMP */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1043 | reg32 = MCHBAR32(GBRCOMPCTL); |
| 1044 | reg32 |= (1 << 8); |
| 1045 | MCHBAR32(GBRCOMPCTL) = reg32; |
| 1046 | |
| 1047 | reg8 = i945_silicon_revision(); |
| 1048 | if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) { |
| 1049 | reg32 = MCHBAR32(GBRCOMPCTL); |
| 1050 | reg32 |= (3 << 5); |
| 1051 | MCHBAR32(GBRCOMPCTL) = reg32; |
| 1052 | } |
| 1053 | } |
| 1054 | |
| 1055 | static void sdram_initialize_system_memory_io(struct sys_info *sysinfo) |
| 1056 | { |
| 1057 | u8 reg8; |
| 1058 | u32 reg32; |
| 1059 | |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 1060 | printk(BIOS_DEBUG, "Initializing System Memory IO...\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1061 | /* Enable Data Half Clock Pushout */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1062 | reg8 = MCHBAR8(C0HCTC); |
| 1063 | reg8 &= ~0x1f; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1064 | reg8 |= (1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1065 | MCHBAR8(C0HCTC) = reg8; |
| 1066 | |
| 1067 | reg8 = MCHBAR8(C1HCTC); |
| 1068 | reg8 &= ~0x1f; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1069 | reg8 |= (1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1070 | MCHBAR8(C1HCTC) = reg8; |
| 1071 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1072 | MCHBAR16(WDLLBYPMODE) &= ~((1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1073 | MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0); |
| 1074 | |
| 1075 | MCHBAR8(C0WDLLCMC) = 0; |
| 1076 | MCHBAR8(C1WDLLCMC) = 0; |
| 1077 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1078 | /* Program RCOMP Settings */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1079 | sdram_program_dram_width(sysinfo); |
| 1080 | |
| 1081 | sdram_rcomp_buffer_strength_and_slew(sysinfo); |
| 1082 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1083 | /* Indicate that RCOMP programming is done */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1084 | reg32 = MCHBAR32(GBRCOMPCTL); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1085 | reg32 &= ~((1 << 29) | (1 << 26) | (3 << 21) | (3 << 2)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1086 | reg32 |= (3 << 27) | (3 << 0); |
| 1087 | MCHBAR32(GBRCOMPCTL) = reg32; |
| 1088 | |
| 1089 | MCHBAR32(GBRCOMPCTL) |= (1 << 10); |
| 1090 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1091 | /* Program DLL Timings */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1092 | sdram_program_dll_timings(sysinfo); |
| 1093 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1094 | /* Force RCOMP cycle */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1095 | sdram_force_rcomp(); |
| 1096 | } |
| 1097 | |
| 1098 | static void sdram_enable_system_memory_io(struct sys_info *sysinfo) |
| 1099 | { |
| 1100 | u32 reg32; |
| 1101 | |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 1102 | printk(BIOS_DEBUG, "Enabling System Memory IO...\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1103 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1104 | reg32 = MCHBAR32(RCVENMT); |
| 1105 | reg32 &= ~(0x3f << 6); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1106 | MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1107 | |
| 1108 | reg32 |= (1 << 11) | (1 << 9); |
| 1109 | MCHBAR32(RCVENMT) = reg32; |
| 1110 | |
| 1111 | reg32 = MCHBAR32(DRTST); |
| 1112 | reg32 |= (1 << 3) | (1 << 2); |
| 1113 | MCHBAR32(DRTST) = reg32; |
| 1114 | |
| 1115 | reg32 = MCHBAR32(DRTST); |
| 1116 | reg32 |= (1 << 6) | (1 << 4); |
| 1117 | MCHBAR32(DRTST) = reg32; |
| 1118 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1119 | asm volatile ("nop; nop;" ::: "memory"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1120 | |
| 1121 | reg32 = MCHBAR32(DRTST); |
| 1122 | |
| 1123 | /* Is channel 0 populated? */ |
| 1124 | if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1125 | sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1126 | reg32 |= (1 << 7) | (1 << 5); |
| 1127 | else |
| 1128 | reg32 |= (1 << 31); |
| 1129 | |
| 1130 | /* Is channel 1 populated? */ |
| 1131 | if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1132 | sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1133 | reg32 |= (1 << 9) | (1 << 8); |
| 1134 | else |
| 1135 | reg32 |= (1 << 30); |
| 1136 | |
| 1137 | MCHBAR32(DRTST) = reg32; |
| 1138 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1139 | /* Activate DRAM Channel IO Buffers */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1140 | if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1141 | sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1142 | reg32 = MCHBAR32(C0DRC1); |
| 1143 | reg32 |= (1 << 8); |
| 1144 | MCHBAR32(C0DRC1) = reg32; |
| 1145 | } |
| 1146 | if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1147 | sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1148 | reg32 = MCHBAR32(C1DRC1); |
| 1149 | reg32 |= (1 << 8); |
| 1150 | MCHBAR32(C1DRC1) = reg32; |
| 1151 | } |
| 1152 | } |
| 1153 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1154 | static int sdram_program_row_boundaries(struct sys_info *sysinfo) |
| 1155 | { |
| 1156 | int i; |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 1157 | int cum0, cum1, tolud, tom, pci_mmio_size; |
| 1158 | const struct device *dev; |
| 1159 | const struct northbridge_intel_i945_config *cfg = NULL; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1160 | |
Paul Menzel | 84283bc | 2014-07-17 08:16:04 +0200 | [diff] [blame] | 1161 | printk(BIOS_DEBUG, "Setting RAM size...\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1162 | |
| 1163 | cum0 = 0; |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 1164 | for (i = 0; i < 2 * DIMM_SOCKETS; i++) { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1165 | cum0 += sysinfo->banksize[i]; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1166 | MCHBAR8(C0DRB0+i) = cum0; |
| 1167 | } |
| 1168 | |
| 1169 | /* Assume we continue in Channel 1 where we stopped in Channel 0 */ |
| 1170 | cum1 = cum0; |
| 1171 | |
| 1172 | /* Exception: Interleaved starts from the beginning */ |
| 1173 | if (sysinfo->interleaved) |
| 1174 | cum1 = 0; |
| 1175 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 1176 | for (i = 0; i < 2 * DIMM_SOCKETS; i++) { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1177 | cum1 += sysinfo->banksize[i + 4]; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1178 | MCHBAR8(C1DRB0+i) = cum1; |
| 1179 | } |
| 1180 | |
| 1181 | /* Set TOLUD Top Of Low Usable DRAM */ |
| 1182 | if (sysinfo->interleaved) |
| 1183 | tolud = (cum0 + cum1) << 1; |
| 1184 | else |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1185 | tolud = (cum1 ? cum1 : cum0) << 1; |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 1186 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1187 | /* The TOM register has a different format */ |
| 1188 | tom = tolud >> 3; |
| 1189 | |
| 1190 | /* Limit the value of TOLUD to leave some space for PCI memory. */ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 1191 | dev = pcidev_on_root(0, 0); |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 1192 | if (dev) |
| 1193 | cfg = dev->chip_info; |
| 1194 | |
| 1195 | /* Don't use pci mmio sizes smaller than 768M */ |
| 1196 | if (!cfg || cfg->pci_mmio_size <= DEFAULT_PCI_MMIO_SIZE) |
| 1197 | pci_mmio_size = DEFAULT_PCI_MMIO_SIZE; |
| 1198 | else |
| 1199 | pci_mmio_size = cfg->pci_mmio_size; |
| 1200 | |
| 1201 | tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1202 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1203 | pci_write_config8(PCI_DEV(0, 0, 0), TOLUD, tolud); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1204 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1205 | printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0)); |
| 1206 | printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0)); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1207 | printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0, 0, 0), TOLUD)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1208 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1209 | pci_write_config16(PCI_DEV(0, 0, 0), TOM, tom); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1210 | |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1214 | static int sdram_set_row_attributes(struct sys_info *sysinfo) |
| 1215 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 1216 | int i; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1217 | u16 dra0 = 0, dra1 = 0, dra = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1218 | |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 1219 | printk(BIOS_DEBUG, "Setting row attributes...\n"); |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1220 | for (i = 0; i < 2 * DIMM_SOCKETS; i++) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1221 | u8 columnsrows; |
| 1222 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1223 | if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1224 | continue; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1225 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1226 | columnsrows = (sysinfo->rows[i] & 0x0f) | (sysinfo->cols[i] & 0xf) << 4; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1227 | |
| 1228 | switch (columnsrows) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1229 | case 0x9d: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1230 | dra = 2; |
| 1231 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1232 | case 0xad: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1233 | dra = 3; |
| 1234 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1235 | case 0xbd: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1236 | dra = 4; |
| 1237 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1238 | case 0xae: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1239 | dra = 3; |
| 1240 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1241 | case 0xbe: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1242 | dra = 4; |
| 1243 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1244 | default: |
| 1245 | die("Unsupported Rows/Columns. (DRA)"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1246 | } |
| 1247 | |
| 1248 | /* Double Sided DIMMs? */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1249 | if (sysinfo->banksize[(2 * i) + 1] != 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1250 | dra = (dra << 4) | dra; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1251 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1252 | if (i < DIMM_SOCKETS) |
| 1253 | dra0 |= (dra << (i*8)); |
| 1254 | else |
| 1255 | dra1 |= (dra << ((i - DIMM_SOCKETS)*8)); |
| 1256 | } |
| 1257 | |
| 1258 | MCHBAR16(C0DRA0) = dra0; |
| 1259 | MCHBAR16(C1DRA0) = dra1; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1260 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1261 | printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0); |
| 1262 | printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1263 | |
| 1264 | return 0; |
| 1265 | } |
| 1266 | |
| 1267 | static void sdram_set_bank_architecture(struct sys_info *sysinfo) |
| 1268 | { |
| 1269 | u32 off32; |
| 1270 | int i; |
| 1271 | |
| 1272 | MCHBAR16(C1BNKARC) &= 0xff00; |
| 1273 | MCHBAR16(C0BNKARC) &= 0xff00; |
| 1274 | |
| 1275 | off32 = C0BNKARC; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1276 | for (i = 0; i < 2 * DIMM_SOCKETS; i++) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1277 | /* Switch to second channel */ |
| 1278 | if (i == DIMM_SOCKETS) |
| 1279 | off32 = C1BNKARC; |
| 1280 | |
| 1281 | if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) |
| 1282 | continue; |
| 1283 | |
| 1284 | if (sysinfo->banks[i] != 8) |
| 1285 | continue; |
| 1286 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1287 | printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1288 | |
| 1289 | if (i & 1) |
| 1290 | MCHBAR16(off32) |= 0x50; |
| 1291 | else |
| 1292 | MCHBAR16(off32) |= 0x05; |
| 1293 | } |
| 1294 | } |
| 1295 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1296 | static void sdram_program_refresh_rate(struct sys_info *sysinfo) |
| 1297 | { |
| 1298 | u32 reg32; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1299 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1300 | if (sysinfo->refresh == REFRESH_7_8US) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1301 | reg32 = (2 << 8); /* Refresh enabled at 7.8us */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1302 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1303 | reg32 = (1 << 8); /* Refresh enabled at 15.6us */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1304 | |
| 1305 | MCHBAR32(C0DRC0) &= ~(7 << 8); |
| 1306 | MCHBAR32(C0DRC0) |= reg32; |
| 1307 | |
| 1308 | MCHBAR32(C1DRC0) &= ~(7 << 8); |
| 1309 | MCHBAR32(C1DRC0) |= reg32; |
| 1310 | } |
| 1311 | |
| 1312 | static void sdram_program_cke_tristate(struct sys_info *sysinfo) |
| 1313 | { |
| 1314 | u32 reg32; |
| 1315 | int i; |
| 1316 | |
| 1317 | reg32 = MCHBAR32(C0DRC1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1318 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1319 | for (i = 0; i < 4; i++) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1320 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1321 | reg32 |= (1 << (16 + i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1322 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1323 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1324 | reg32 |= (1 << 12); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1325 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1326 | reg32 |= (1 << 11); |
| 1327 | MCHBAR32(C0DRC1) = reg32; |
| 1328 | |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1329 | /* Do we have to do this if we're in Single Channel Mode? */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1330 | reg32 = MCHBAR32(C1DRC1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1331 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1332 | for (i = 4; i < 8; i++) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1333 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1334 | reg32 |= (1 << (12 + i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1335 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1336 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1337 | reg32 |= (1 << 12); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1338 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1339 | reg32 |= (1 << 11); |
| 1340 | MCHBAR32(C1DRC1) = reg32; |
| 1341 | } |
| 1342 | |
| 1343 | static void sdram_program_odt_tristate(struct sys_info *sysinfo) |
| 1344 | { |
| 1345 | u32 reg32; |
| 1346 | int i; |
| 1347 | |
| 1348 | reg32 = MCHBAR32(C0DRC2); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1349 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1350 | for (i = 0; i < 4; i++) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1351 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1352 | reg32 |= (1 << (24 + i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1353 | } |
| 1354 | MCHBAR32(C0DRC2) = reg32; |
| 1355 | |
| 1356 | reg32 = MCHBAR32(C1DRC2); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1357 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1358 | for (i = 4; i < 8; i++) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1359 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1360 | reg32 |= (1 << (20 + i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1361 | } |
| 1362 | MCHBAR32(C1DRC2) = reg32; |
| 1363 | } |
| 1364 | |
| 1365 | static void sdram_set_timing_and_control(struct sys_info *sysinfo) |
| 1366 | { |
Arthur Heymans | 2502723 | 2017-02-12 23:34:39 +0100 | [diff] [blame] | 1367 | u32 reg32, tRD_min; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1368 | u32 tWTR; |
| 1369 | u32 temp_drt; |
| 1370 | int i, page_size; |
| 1371 | |
Edward O'Callaghan | 2f237c1 | 2014-05-25 06:24:39 +1000 | [diff] [blame] | 1372 | static const u8 cas_table[] = { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1373 | 2, 1, 0, 3 |
| 1374 | }; |
| 1375 | |
| 1376 | reg32 = MCHBAR32(C0DRC0); |
| 1377 | reg32 |= (1 << 2); /* Burst Length 8 */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1378 | reg32 &= ~((1 << 13) | (1 << 12)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1379 | MCHBAR32(C0DRC0) = reg32; |
| 1380 | |
| 1381 | reg32 = MCHBAR32(C1DRC0); |
| 1382 | reg32 |= (1 << 2); /* Burst Length 8 */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1383 | reg32 &= ~((1 << 13) | (1 << 12)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1384 | MCHBAR32(C1DRC0) = reg32; |
| 1385 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1386 | if (!sysinfo->dual_channel && sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1387 | reg32 = MCHBAR32(C0DRC0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1388 | reg32 |= (1 << 15); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1389 | MCHBAR32(C0DRC0) = reg32; |
| 1390 | } |
| 1391 | |
| 1392 | sdram_program_refresh_rate(sysinfo); |
| 1393 | |
| 1394 | sdram_program_cke_tristate(sysinfo); |
| 1395 | |
| 1396 | sdram_program_odt_tristate(sysinfo); |
| 1397 | |
| 1398 | /* Calculate DRT0 */ |
| 1399 | |
| 1400 | temp_drt = 0; |
| 1401 | |
| 1402 | /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */ |
| 1403 | reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr; |
| 1404 | temp_drt |= (reg32 << 28); |
| 1405 | |
| 1406 | /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */ |
| 1407 | reg32 += sysinfo->trp; |
| 1408 | temp_drt |= (reg32 << 4); |
| 1409 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1410 | if (sysinfo->memory_frequency == 667) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1411 | tWTR = 3; /* 667MHz */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1412 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1413 | tWTR = 2; /* 400 and 533 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1414 | |
| 1415 | /* B2B Write to Read Command Spacing */ |
| 1416 | reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR; |
| 1417 | temp_drt |= (reg32 << 24); |
| 1418 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1419 | /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1420 | temp_drt |= ((1 << 22) | (3 << 20) | (1 << 18) | (0 << 16)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1421 | |
Arthur Heymans | 2502723 | 2017-02-12 23:34:39 +0100 | [diff] [blame] | 1422 | /* |
| 1423 | * tRD is the delay the memory controller is waiting on the FSB, |
| 1424 | * in mclk domain. |
| 1425 | * This parameter is important for stability and performance. |
| 1426 | * Those values might not be optimal but seem stable. |
| 1427 | */ |
| 1428 | tRD_min = sysinfo->cas; |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1429 | switch (sysinfo->fsb_frequency) { |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1430 | case 533: |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1431 | break; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1432 | case 667: |
| 1433 | tRD_min += 1; |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1434 | break; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1435 | case 800: |
| 1436 | tRD_min += 2; |
| 1437 | break; |
| 1438 | case 1066: |
| 1439 | tRD_min += 3; |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1440 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1441 | } |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1442 | |
Arthur Heymans | 2502723 | 2017-02-12 23:34:39 +0100 | [diff] [blame] | 1443 | temp_drt |= (tRD_min << 11); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1444 | |
| 1445 | /* Read Auto Precharge to Activate */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1446 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1447 | temp_drt |= (8 << 0); |
| 1448 | |
| 1449 | MCHBAR32(C0DRT0) = temp_drt; |
| 1450 | MCHBAR32(C1DRT0) = temp_drt; |
| 1451 | |
| 1452 | /* Calculate DRT1 */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1453 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1454 | temp_drt = MCHBAR32(C0DRT1) & 0x00020088; |
| 1455 | |
| 1456 | /* DRAM RASB Precharge */ |
| 1457 | temp_drt |= (sysinfo->trp - 2) << 0; |
| 1458 | |
| 1459 | /* DRAM RASB to CASB Delay */ |
| 1460 | temp_drt |= (sysinfo->trcd - 2) << 4; |
| 1461 | |
| 1462 | /* CASB Latency */ |
| 1463 | temp_drt |= (cas_table[sysinfo->cas - 3]) << 8; |
| 1464 | |
| 1465 | /* Refresh Cycle Time */ |
| 1466 | temp_drt |= (sysinfo->trfc) << 10; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1467 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1468 | /* Pre-All to Activate Delay */ |
| 1469 | temp_drt |= (0 << 16); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1470 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1471 | /* Precharge to Precharge Delay stays at 1 clock */ |
| 1472 | temp_drt |= (0 << 18); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1473 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1474 | /* Activate to Precharge Delay */ |
| 1475 | temp_drt |= (sysinfo->tras << 19); |
| 1476 | |
| 1477 | /* Read to Precharge (tRTP) */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1478 | if (sysinfo->memory_frequency == 667) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1479 | temp_drt |= (1 << 28); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1480 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1481 | temp_drt |= (0 << 28); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1482 | |
| 1483 | /* Determine page size */ |
| 1484 | reg32 = 0; |
| 1485 | page_size = 1; /* Default: 1k pagesize */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1486 | for (i = 0; i < 2*DIMM_SOCKETS; i++) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1487 | if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1488 | sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1489 | page_size = 2; /* 2k pagesize */ |
| 1490 | } |
| 1491 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1492 | if (sysinfo->memory_frequency == 533 && page_size == 2) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1493 | reg32 = 1; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1494 | if (sysinfo->memory_frequency == 667) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1495 | reg32 = page_size; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1496 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1497 | temp_drt |= (reg32 << 30); |
| 1498 | |
| 1499 | MCHBAR32(C0DRT1) = temp_drt; |
| 1500 | MCHBAR32(C1DRT1) = temp_drt; |
| 1501 | |
| 1502 | /* Program DRT2 */ |
| 1503 | reg32 = MCHBAR32(C0DRT2); |
| 1504 | reg32 &= ~(1 << 8); |
| 1505 | MCHBAR32(C0DRT2) = reg32; |
| 1506 | |
| 1507 | reg32 = MCHBAR32(C1DRT2); |
| 1508 | reg32 &= ~(1 << 8); |
| 1509 | MCHBAR32(C1DRT2) = reg32; |
| 1510 | |
| 1511 | /* Calculate DRT3 */ |
| 1512 | temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff; |
| 1513 | |
| 1514 | /* Get old tRFC value */ |
| 1515 | reg32 = MCHBAR32(C0DRT1) >> 10; |
| 1516 | reg32 &= 0x3f; |
| 1517 | |
| 1518 | /* 788nS - tRFC */ |
| 1519 | switch (sysinfo->memory_frequency) { |
| 1520 | case 400: /* 5nS */ |
| 1521 | reg32 = ((78800 / 500) - reg32) & 0x1ff; |
| 1522 | reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */ |
| 1523 | break; |
| 1524 | case 533: /* 3.75nS */ |
| 1525 | reg32 = ((78800 / 375) - reg32) & 0x1ff; |
| 1526 | reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */ |
| 1527 | break; |
| 1528 | case 667: /* 3nS */ |
| 1529 | reg32 = ((78800 / 300) - reg32) & 0x1ff; |
| 1530 | reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */ |
| 1531 | break; |
| 1532 | } |
| 1533 | |
| 1534 | temp_drt |= reg32; |
| 1535 | |
| 1536 | MCHBAR32(C0DRT3) = temp_drt; |
| 1537 | MCHBAR32(C1DRT3) = temp_drt; |
| 1538 | } |
| 1539 | |
| 1540 | static void sdram_set_channel_mode(struct sys_info *sysinfo) |
| 1541 | { |
| 1542 | u32 reg32; |
| 1543 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1544 | printk(BIOS_DEBUG, "Setting mode of operation for memory channels..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1545 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1546 | if (sdram_capabilities_interleave() && |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1547 | ((sysinfo->banksize[0] + sysinfo->banksize[1] + |
| 1548 | sysinfo->banksize[2] + sysinfo->banksize[3]) == |
| 1549 | (sysinfo->banksize[4] + sysinfo->banksize[5] + |
| 1550 | sysinfo->banksize[6] + sysinfo->banksize[7]))) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1551 | /* Both channels equipped with DIMMs of the same size */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1552 | sysinfo->interleaved = 1; |
| 1553 | } else { |
| 1554 | sysinfo->interleaved = 0; |
| 1555 | } |
| 1556 | |
| 1557 | reg32 = MCHBAR32(DCC); |
| 1558 | reg32 &= ~(7 << 0); |
| 1559 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 1560 | if (sysinfo->interleaved) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1561 | /* Dual Channel Interleaved */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1562 | printk(BIOS_DEBUG, "Dual Channel Interleaved.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1563 | reg32 |= (1 << 1); |
| 1564 | } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED && |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1565 | sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1566 | /* Channel 1 only */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1567 | printk(BIOS_DEBUG, "Single Channel 1 only.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1568 | reg32 |= (1 << 2); |
Elyes HAOUAS | 75da1fb | 2017-02-16 18:59:13 +0100 | [diff] [blame] | 1569 | } else if (sdram_capabilities_dual_channel() && |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1570 | (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || |
| 1571 | sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) { |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 1572 | /* Dual Channel Asymmetric */ |
| 1573 | printk(BIOS_DEBUG, "Dual Channel Asymmetric.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1574 | reg32 |= (1 << 0); |
| 1575 | } else { |
| 1576 | /* All bits 0 means Single Channel 0 operation */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1577 | printk(BIOS_DEBUG, "Single Channel 0 only.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1578 | } |
| 1579 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1580 | /* Now disable channel XORing */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1581 | reg32 |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1582 | |
| 1583 | MCHBAR32(DCC) = reg32; |
| 1584 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1585 | PRINTK_DEBUG("DCC = 0x%08x\n", MCHBAR32(DCC)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1586 | } |
| 1587 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1588 | static void sdram_program_pll_settings(struct sys_info *sysinfo) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1589 | { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1590 | MCHBAR32(PLLMON) = 0x80800000; |
| 1591 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1592 | sysinfo->fsb_frequency = fsbclk(); |
Peter Stuge | 76d9143 | 2010-10-01 10:02:33 +0000 | [diff] [blame] | 1593 | if (sysinfo->fsb_frequency == 0xffff) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1594 | die("Unsupported FSB speed"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1595 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1596 | /* Program CPCTL according to FSB speed */ |
| 1597 | /* Only write the lower byte */ |
| 1598 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1599 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1600 | MCHBAR8(CPCTL) = 0x90; |
| 1601 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1602 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1603 | MCHBAR8(CPCTL) = 0x95; |
| 1604 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1605 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1606 | MCHBAR8(CPCTL) = 0x8d; |
| 1607 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1608 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1609 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1610 | MCHBAR16(CPCTL) &= ~(1 << 11); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1611 | |
Paul Menzel | 0ce5ebf | 2013-10-21 21:22:09 +0200 | [diff] [blame] | 1612 | MCHBAR16(CPCTL); /* Read back register to activate settings */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1613 | } |
| 1614 | |
| 1615 | static void sdram_program_graphics_frequency(struct sys_info *sysinfo) |
| 1616 | { |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1617 | u8 reg8; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1618 | u16 reg16; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1619 | u8 freq, second_vco, voltage; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1620 | |
| 1621 | #define CRCLK_166MHz 0x00 |
| 1622 | #define CRCLK_200MHz 0x01 |
| 1623 | #define CRCLK_250MHz 0x03 |
| 1624 | #define CRCLK_400MHz 0x05 |
| 1625 | |
| 1626 | #define CDCLK_200MHz 0x00 |
| 1627 | #define CDCLK_320MHz 0x40 |
| 1628 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1629 | #define VOLTAGE_1_05 0x00 |
| 1630 | #define VOLTAGE_1_50 0x01 |
| 1631 | |
Paul Menzel | daf9e50 | 2014-07-15 23:49:16 +0200 | [diff] [blame] | 1632 | printk(BIOS_DEBUG, "Setting Graphics Frequency...\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1633 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1634 | printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1635 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1636 | voltage = VOLTAGE_1_05; |
| 1637 | if (MCHBAR32(DFT_STRAP1) & (1 << 20)) |
| 1638 | voltage = VOLTAGE_1_50; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1639 | printk(BIOS_DEBUG, "Voltage: %s ", (voltage == VOLTAGE_1_05)?"1.05V":"1.5V"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1640 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1641 | /* Gate graphics hardware for frequency change */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1642 | reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1643 | pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1644 | |
| 1645 | /* Get graphics frequency capabilities */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1646 | reg8 = sdram_capabilities_core_frequencies(); |
| 1647 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1648 | freq = CRCLK_250MHz; |
| 1649 | switch (reg8) { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1650 | case GFX_FREQUENCY_CAP_ALL: |
| 1651 | if (voltage == VOLTAGE_1_05) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1652 | freq = CRCLK_250MHz; |
| 1653 | else |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1654 | freq = CRCLK_400MHz; /* 1.5V requires 400MHz */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1655 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1656 | case GFX_FREQUENCY_CAP_250MHZ: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1657 | freq = CRCLK_250MHz; |
| 1658 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1659 | case GFX_FREQUENCY_CAP_200MHZ: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1660 | freq = CRCLK_200MHz; |
| 1661 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1662 | case GFX_FREQUENCY_CAP_166MHZ: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1663 | freq = CRCLK_166MHz; |
| 1664 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1665 | } |
| 1666 | |
| 1667 | if (freq != CRCLK_400MHz) { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1668 | /* What chipset are we? Force 166MHz for GMS */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1669 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1670 | if (reg8 == 2) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1671 | freq = CRCLK_166MHz; |
| 1672 | } |
| 1673 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1674 | printk(BIOS_DEBUG, "Render: "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1675 | switch (freq) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1676 | case CRCLK_166MHz: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1677 | printk(BIOS_DEBUG, "166MHz"); |
| 1678 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1679 | case CRCLK_200MHz: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1680 | printk(BIOS_DEBUG, "200MHz"); |
| 1681 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1682 | case CRCLK_250MHz: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1683 | printk(BIOS_DEBUG, "250MHz"); |
| 1684 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1685 | case CRCLK_400MHz: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1686 | printk(BIOS_DEBUG, "400MHz"); |
| 1687 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1688 | } |
| 1689 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1690 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1691 | sysinfo->mvco4x = 1; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1692 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1693 | sysinfo->mvco4x = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1694 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1695 | second_vco = 0; |
| 1696 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1697 | if (voltage == VOLTAGE_1_50) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1698 | second_vco = 1; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1699 | } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1700 | u16 mem = sysinfo->memory_frequency; |
| 1701 | u16 fsb = sysinfo->fsb_frequency; |
| 1702 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1703 | if ((fsb == 667 && mem == 533) || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1704 | (fsb == 533 && mem == 533) || |
| 1705 | (fsb == 533 && mem == 400)) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1706 | second_vco = 1; |
| 1707 | } |
| 1708 | |
| 1709 | if (fsb == 667 && mem == 533) |
| 1710 | sysinfo->mvco4x = 1; |
| 1711 | } |
| 1712 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1713 | if (second_vco) |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1714 | sysinfo->clkcfg_bit7 = 1; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1715 | else |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1716 | sysinfo->clkcfg_bit7 = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1717 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1718 | /* Graphics Core Render Clock */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1719 | reg16 = pci_read_config16(PCI_DEV(0, 2, 0), GCFC); |
| 1720 | reg16 &= ~((7 << 0) | (1 << 13)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1721 | reg16 |= freq; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1722 | pci_write_config16(PCI_DEV(0, 2, 0), GCFC, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1723 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1724 | /* Graphics Core Display Clock */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1725 | reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC); |
| 1726 | reg8 &= ~((1<<7) | (7<<4)); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1727 | |
| 1728 | if (voltage == VOLTAGE_1_05) { |
| 1729 | reg8 |= CDCLK_200MHz; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1730 | printk(BIOS_DEBUG, " Display: 200MHz\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1731 | } else { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1732 | reg8 |= CDCLK_320MHz; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1733 | printk(BIOS_DEBUG, " Display: 320MHz\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1734 | } |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1735 | pci_write_config8(PCI_DEV(0, 2, 0), GCFC, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1736 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1737 | reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1738 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1739 | reg8 |= (1<<3) | (1<<1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1740 | pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1741 | |
| 1742 | reg8 |= 0x0f; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1743 | pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1744 | |
| 1745 | /* Ungate core render and display clocks */ |
| 1746 | reg8 &= 0xf0; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1747 | pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1748 | } |
| 1749 | |
| 1750 | static void sdram_program_memory_frequency(struct sys_info *sysinfo) |
| 1751 | { |
| 1752 | u32 clkcfg; |
| 1753 | u8 reg8; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1754 | u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1755 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1756 | printk(BIOS_DEBUG, "Setting Memory Frequency... "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1757 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1758 | clkcfg = MCHBAR32(CLKCFG); |
| 1759 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1760 | printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", clkcfg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1761 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1762 | clkcfg &= ~((1 << 12) | (1 << 7) | (7 << 4)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1763 | |
| 1764 | if (sysinfo->mvco4x) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1765 | printk(BIOS_DEBUG, "MVCO 4x, "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1766 | clkcfg &= ~(1 << 12); |
| 1767 | } |
| 1768 | |
| 1769 | if (sysinfo->clkcfg_bit7) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1770 | printk(BIOS_DEBUG, "second VCO, "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1771 | clkcfg |= (1 << 7); |
| 1772 | } |
| 1773 | |
| 1774 | switch (sysinfo->memory_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1775 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1776 | clkcfg |= ((1 + offset) << 4); |
| 1777 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1778 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1779 | clkcfg |= ((2 + offset) << 4); |
| 1780 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1781 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1782 | clkcfg |= ((3 + offset) << 4); |
| 1783 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1784 | default: |
| 1785 | die("Target Memory Frequency Error"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1786 | } |
| 1787 | |
| 1788 | if (MCHBAR32(CLKCFG) == clkcfg) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1789 | printk(BIOS_DEBUG, "ok (unchanged)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1790 | return; |
| 1791 | } |
| 1792 | |
| 1793 | MCHBAR32(CLKCFG) = clkcfg; |
| 1794 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1795 | /* Make sure the following code is in the cache before we execute it. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1796 | goto cache_code; |
| 1797 | vco_update: |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 1798 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1799 | reg8 &= ~(1 << 7); |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 1800 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1801 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1802 | clkcfg &= ~(1 << 10); |
| 1803 | MCHBAR32(CLKCFG) = clkcfg; |
| 1804 | clkcfg |= (1 << 10); |
| 1805 | MCHBAR32(CLKCFG) = clkcfg; |
| 1806 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1807 | asm volatile ( |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1808 | " movl $0x100, %%ecx\n" |
| 1809 | "delay_update:\n" |
| 1810 | " nop\n" |
| 1811 | " nop\n" |
| 1812 | " nop\n" |
| 1813 | " nop\n" |
| 1814 | " loop delay_update\n" |
| 1815 | : /* No outputs */ |
| 1816 | : /* No inputs */ |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1817 | : "%ecx", "memory" |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1818 | ); |
| 1819 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1820 | clkcfg &= ~(1 << 10); |
| 1821 | MCHBAR32(CLKCFG) = clkcfg; |
| 1822 | |
| 1823 | goto out; |
| 1824 | cache_code: |
| 1825 | goto vco_update; |
| 1826 | out: |
| 1827 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1828 | printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", MCHBAR32(CLKCFG)); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1829 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1830 | } |
| 1831 | |
| 1832 | static void sdram_program_clock_crossing(void) |
| 1833 | { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1834 | int idx = 0; |
| 1835 | |
| 1836 | /** |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1837 | * We add the indices according to our clocks from CLKCFG. |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1838 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1839 | #if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1840 | static const u32 data_clock_crossing[] = { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1841 | 0x00100401, 0x00000000, /* DDR400 FSB400 */ |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1842 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1843 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1844 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1845 | 0x08040120, 0x00000000, /* DDR400 FSB533 */ |
| 1846 | 0x00100401, 0x00000000, /* DDR533 FSB533 */ |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1847 | 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1848 | |
| 1849 | 0x04020120, 0x00000010, /* DDR400 FSB667 */ |
| 1850 | 0x10040280, 0x00000040, /* DDR533 FSB667 */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1851 | 0x00100401, 0x00000000, /* DDR667 FSB667 */ |
| 1852 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1853 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1854 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1855 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1856 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1857 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1858 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1859 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1860 | }; |
| 1861 | |
| 1862 | static const u32 command_clock_crossing[] = { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1863 | 0x04020208, 0x00000000, /* DDR400 FSB400 */ |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1864 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1865 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1866 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1867 | 0x00060108, 0x00000000, /* DDR400 FSB533 */ |
| 1868 | 0x04020108, 0x00000000, /* DDR533 FSB533 */ |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1869 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1870 | |
| 1871 | 0x00040318, 0x00000000, /* DDR400 FSB667 */ |
| 1872 | 0x04020118, 0x00000000, /* DDR533 FSB667 */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1873 | 0x02010804, 0x00000000, /* DDR667 FSB667 */ |
| 1874 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1875 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1876 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1877 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1878 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1879 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1880 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1881 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1882 | }; |
| 1883 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1884 | #elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1885 | /* i945 G/P */ |
| 1886 | static const u32 data_clock_crossing[] = { |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1887 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1888 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1889 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1890 | |
| 1891 | 0x10080201, 0x00000000, /* DDR400 FSB533 */ |
| 1892 | 0x00100401, 0x00000000, /* DDR533 FSB533 */ |
Patrick Georgi | 682ea3c | 2010-04-20 15:52:57 +0000 | [diff] [blame] | 1893 | 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1894 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1895 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1896 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1897 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1898 | |
| 1899 | 0x04020108, 0x00000000, /* DDR400 FSB800 */ |
| 1900 | 0x00020108, 0x00000000, /* DDR533 FSB800 */ |
| 1901 | 0x00080201, 0x00000000, /* DDR667 FSB800 */ |
| 1902 | |
| 1903 | 0x00010402, 0x00000000, /* DDR400 FSB1066 */ |
| 1904 | 0x04020108, 0x00000000, /* DDR533 FSB1066 */ |
| 1905 | 0x08040110, 0x00000000, /* DDR667 FSB1066 */ |
| 1906 | }; |
| 1907 | |
| 1908 | static const u32 command_clock_crossing[] = { |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1909 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1910 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1911 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1912 | |
| 1913 | 0x00010800, 0x00000402, /* DDR400 FSB533 */ |
| 1914 | 0x01000400, 0x00000200, /* DDR533 FSB533 */ |
Patrick Georgi | 682ea3c | 2010-04-20 15:52:57 +0000 | [diff] [blame] | 1915 | 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1916 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1917 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1918 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1919 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1920 | |
| 1921 | 0x02010804, 0x00000000, /* DDR400 FSB800 */ |
| 1922 | 0x00010402, 0x00000000, /* DDR533 FSB800 */ |
Arthur Heymans | 8b6df62 | 2016-10-16 10:58:01 +0200 | [diff] [blame] | 1923 | 0x04020130, 0x00000008, /* DDR667 FSB800 */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1924 | |
| 1925 | 0x00020904, 0x00000000, /* DDR400 FSB1066 */ |
| 1926 | 0x02010804, 0x00000000, /* DDR533 FSB1066 */ |
| 1927 | 0x180601c0, 0x00000020, /* DDR667 FSB1066 */ |
| 1928 | }; |
| 1929 | #endif |
| 1930 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1931 | printk(BIOS_DEBUG, "Programming Clock Crossing..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1932 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1933 | printk(BIOS_DEBUG, "MEM="); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1934 | switch (memclk()) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1935 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1936 | printk(BIOS_DEBUG, "400"); |
| 1937 | idx += 0; |
| 1938 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1939 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1940 | printk(BIOS_DEBUG, "533"); |
| 1941 | idx += 2; |
| 1942 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1943 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1944 | printk(BIOS_DEBUG, "667"); |
| 1945 | idx += 4; |
| 1946 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1947 | default: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1948 | printk(BIOS_DEBUG, "RSVD %x", memclk()); |
| 1949 | return; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1950 | } |
| 1951 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1952 | printk(BIOS_DEBUG, " FSB="); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1953 | switch (fsbclk()) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1954 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1955 | printk(BIOS_DEBUG, "400"); |
| 1956 | idx += 0; |
| 1957 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1958 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1959 | printk(BIOS_DEBUG, "533"); |
| 1960 | idx += 6; |
| 1961 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1962 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1963 | printk(BIOS_DEBUG, "667"); |
| 1964 | idx += 12; |
| 1965 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1966 | case 800: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1967 | printk(BIOS_DEBUG, "800"); |
| 1968 | idx += 18; |
| 1969 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1970 | case 1066: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1971 | printk(BIOS_DEBUG, "1066"); |
| 1972 | idx += 24; |
| 1973 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1974 | default: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1975 | printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); |
| 1976 | return; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1977 | } |
| 1978 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1979 | if (command_clock_crossing[idx] == 0xffffffff) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1980 | printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1981 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1982 | MCHBAR32(CCCFT + 0) = command_clock_crossing[idx]; |
| 1983 | MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1]; |
| 1984 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1985 | MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx]; |
| 1986 | MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1]; |
| 1987 | MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx]; |
| 1988 | MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1]; |
| 1989 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1990 | printk(BIOS_DEBUG, "... ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1991 | } |
| 1992 | |
| 1993 | static void sdram_disable_fast_dispatch(void) |
| 1994 | { |
| 1995 | u32 reg32; |
| 1996 | |
| 1997 | reg32 = MCHBAR32(FSBPMC3); |
| 1998 | reg32 |= (1 << 1); |
| 1999 | MCHBAR32(FSBPMC3) = reg32; |
| 2000 | |
| 2001 | reg32 = MCHBAR32(SBTEST); |
| 2002 | reg32 |= (3 << 1); |
| 2003 | MCHBAR32(SBTEST) = reg32; |
| 2004 | } |
| 2005 | |
| 2006 | static void sdram_pre_jedec_initialization(void) |
| 2007 | { |
| 2008 | u32 reg32; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2009 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2010 | reg32 = MCHBAR32(WCC); |
| 2011 | reg32 &= 0x113ff3ff; |
| 2012 | reg32 |= (4 << 29) | (3 << 25) | (1 << 10); |
| 2013 | MCHBAR32(WCC) = reg32; |
| 2014 | |
| 2015 | MCHBAR32(SMVREFC) |= (1 << 6); |
| 2016 | |
| 2017 | MCHBAR32(MMARB0) &= ~(3 << 17); |
| 2018 | MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16); |
| 2019 | |
| 2020 | MCHBAR32(MMARB1) &= ~(7 << 8); |
| 2021 | MCHBAR32(MMARB1) |= (3 << 8); |
| 2022 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2023 | /* Adaptive Idle Timer Control */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2024 | MCHBAR32(C0AIT) = 0x000006c4; |
| 2025 | MCHBAR32(C0AIT+4) = 0x871a066d; |
| 2026 | |
| 2027 | MCHBAR32(C1AIT) = 0x000006c4; |
| 2028 | MCHBAR32(C1AIT+4) = 0x871a066d; |
| 2029 | } |
| 2030 | |
| 2031 | #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE (0xd4 << 24) |
| 2032 | #define EA_DUALCHANNEL_XOR_BANK_MODE (0xf4 << 24) |
| 2033 | #define EA_DUALCHANNEL_BANK_RANK_MODE (0xc2 << 24) |
| 2034 | #define EA_DUALCHANNEL_BANK_MODE (0xe2 << 24) |
| 2035 | #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE (0x91 << 24) |
| 2036 | #define EA_SINGLECHANNEL_XOR_BANK_MODE (0xb1 << 24) |
| 2037 | #define EA_SINGLECHANNEL_BANK_RANK_MODE (0x80 << 24) |
| 2038 | #define EA_SINGLECHANNEL_BANK_MODE (0xa0 << 24) |
| 2039 | |
| 2040 | static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo) |
| 2041 | { |
| 2042 | u32 chan0 = 0, chan1 = 0; |
Paul Menzel | d789b658 | 2020-03-14 11:50:34 +0100 | [diff] [blame] | 2043 | bool chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2044 | |
Paul Menzel | 842dd33 | 2020-03-14 10:37:40 +0100 | [diff] [blame] | 2045 | chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2046 | sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); |
Elyes HAOUAS | 308aeff | 2017-02-24 12:53:07 +0100 | [diff] [blame] | 2047 | chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2048 | sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2049 | chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]); |
| 2050 | chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]); |
| 2051 | |
| 2052 | if (sdram_capabilities_enhanced_addressing_xor()) { |
| 2053 | if (!sysinfo->interleaved) { |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 2054 | /* Single Channel & Dual Channel Asymmetric */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2055 | if (chan0_populated) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2056 | if (chan0_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2057 | chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2058 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2059 | chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2060 | } |
| 2061 | if (chan1_populated) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2062 | if (chan1_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2063 | chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2064 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2065 | chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2066 | } |
| 2067 | } else { |
| 2068 | /* Interleaved has always both channels populated */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2069 | if (chan0_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2070 | chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2071 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2072 | chan0 = EA_DUALCHANNEL_XOR_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2073 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2074 | if (chan1_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2075 | chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2076 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2077 | chan1 = EA_DUALCHANNEL_XOR_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2078 | } |
| 2079 | } else { |
| 2080 | if (!sysinfo->interleaved) { |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 2081 | /* Single Channel & Dual Channel Asymmetric */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2082 | if (chan0_populated) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2083 | if (chan0_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2084 | chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2085 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2086 | chan0 = EA_SINGLECHANNEL_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2087 | } |
| 2088 | if (chan1_populated) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2089 | if (chan1_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2090 | chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2091 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2092 | chan1 = EA_SINGLECHANNEL_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2093 | } |
| 2094 | } else { |
| 2095 | /* Interleaved has always both channels populated */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2096 | if (chan0_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2097 | chan0 = EA_DUALCHANNEL_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2098 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2099 | chan0 = EA_DUALCHANNEL_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2100 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2101 | if (chan1_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2102 | chan1 = EA_DUALCHANNEL_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2103 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2104 | chan1 = EA_DUALCHANNEL_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2105 | } |
| 2106 | } |
| 2107 | |
| 2108 | MCHBAR32(C0DRC1) &= 0x00ffffff; |
| 2109 | MCHBAR32(C0DRC1) |= chan0; |
| 2110 | MCHBAR32(C1DRC1) &= 0x00ffffff; |
| 2111 | MCHBAR32(C1DRC1) |= chan1; |
| 2112 | } |
| 2113 | |
| 2114 | static void sdram_post_jedec_initialization(struct sys_info *sysinfo) |
| 2115 | { |
| 2116 | u32 reg32; |
| 2117 | |
| 2118 | /* Enable Channel XORing for Dual Channel Interleave */ |
| 2119 | if (sysinfo->interleaved) { |
| 2120 | reg32 = MCHBAR32(DCC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2121 | reg32 &= ~(1 << 10); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 2122 | reg32 |= (1 << 9); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2123 | MCHBAR32(DCC) = reg32; |
| 2124 | } |
| 2125 | |
| 2126 | /* DRAM mode optimizations */ |
| 2127 | sdram_enhanced_addressing_mode(sysinfo); |
| 2128 | |
| 2129 | reg32 = MCHBAR32(FSBPMC3); |
| 2130 | reg32 &= ~(1 << 1); |
| 2131 | MCHBAR32(FSBPMC3) = reg32; |
| 2132 | |
| 2133 | reg32 = MCHBAR32(SBTEST); |
| 2134 | reg32 &= ~(1 << 2); |
| 2135 | MCHBAR32(SBTEST) = reg32; |
| 2136 | |
| 2137 | reg32 = MCHBAR32(SBOCC); |
| 2138 | reg32 &= 0xffbdb6ff; |
| 2139 | reg32 |= (0xbdb6 << 8) | (1 << 0); |
| 2140 | MCHBAR32(SBOCC) = reg32; |
| 2141 | } |
| 2142 | |
| 2143 | static void sdram_power_management(struct sys_info *sysinfo) |
| 2144 | { |
| 2145 | u8 reg8; |
| 2146 | u16 reg16; |
| 2147 | u32 reg32; |
| 2148 | int integrated_graphics = 1; |
| 2149 | int i; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2150 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2151 | reg32 = MCHBAR32(C0DRT2); |
| 2152 | reg32 &= 0xffffff00; |
| 2153 | /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2154 | reg32 |= (1 << 5) | (1 << 4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2155 | MCHBAR32(C0DRT2) = reg32; |
| 2156 | |
| 2157 | reg32 = MCHBAR32(C1DRT2); |
| 2158 | reg32 &= 0xffffff00; |
| 2159 | /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2160 | reg32 |= (1 << 5) | (1 << 4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2161 | MCHBAR32(C1DRT2) = reg32; |
| 2162 | |
| 2163 | reg32 = MCHBAR32(C0DRC1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2164 | |
| 2165 | reg32 |= (1 << 12) | (1 << 11); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2166 | MCHBAR32(C0DRC1) = reg32; |
| 2167 | |
| 2168 | reg32 = MCHBAR32(C1DRC1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2169 | |
| 2170 | reg32 |= (1 << 12) | (1 << 11); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2171 | MCHBAR32(C1DRC1) = reg32; |
| 2172 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2173 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 2174 | if (i945_silicon_revision() > 1) { |
| 2175 | /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ |
| 2176 | u16 peg_bits = (1 << 5) | (1 << 0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2177 | |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 2178 | MCHBAR16(UPMC1) = 0x1010 | peg_bits; |
| 2179 | } else { |
| 2180 | /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ |
| 2181 | u16 peg_bits = (1 << 5) | (1 << 0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2182 | |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 2183 | /* Rev 0 and 1 */ |
| 2184 | MCHBAR16(UPMC1) = 0x0010 | peg_bits; |
| 2185 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2186 | } |
| 2187 | |
| 2188 | reg16 = MCHBAR16(UPMC2); |
| 2189 | reg16 &= 0xfc00; |
| 2190 | reg16 |= 0x0100; |
| 2191 | MCHBAR16(UPMC2) = reg16; |
| 2192 | |
| 2193 | MCHBAR32(UPMC3) = 0x000f06ff; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2194 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 2195 | for (i = 0; i < 5; i++) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2196 | MCHBAR32(UPMC3) &= ~(1 << 16); |
| 2197 | MCHBAR32(UPMC3) |= (1 << 16); |
| 2198 | } |
| 2199 | |
| 2200 | MCHBAR32(GIPMC1) = 0x8000000c; |
| 2201 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2202 | reg16 = MCHBAR16(CPCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2203 | reg16 &= ~(7 << 11); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2204 | if (i945_silicon_revision() > 2) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2205 | reg16 |= (6 << 11); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2206 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2207 | reg16 |= (4 << 11); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2208 | MCHBAR16(CPCTL) = reg16; |
| 2209 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 2210 | #if 0 |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2211 | if ((MCHBAR32(ECO) & (1 << 16)) != 0) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 2212 | #else |
| 2213 | if (i945_silicon_revision() != 0) { |
| 2214 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2215 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2216 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2217 | MCHBAR32(HGIPMC2) = 0x0d590d59; |
| 2218 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2219 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2220 | MCHBAR32(HGIPMC2) = 0x155b155b; |
| 2221 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2222 | } |
| 2223 | } else { |
| 2224 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2225 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2226 | MCHBAR32(HGIPMC2) = 0x09c409c4; |
| 2227 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2228 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2229 | MCHBAR32(HGIPMC2) = 0x0fa00fa0; |
| 2230 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2231 | } |
| 2232 | } |
| 2233 | |
| 2234 | MCHBAR32(FSBPMC1) = 0x8000000c; |
| 2235 | |
| 2236 | reg32 = MCHBAR32(C2C3TT); |
| 2237 | reg32 &= 0xffff0000; |
| 2238 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2239 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2240 | reg32 |= 0x0600; |
| 2241 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2242 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2243 | reg32 |= 0x0480; |
| 2244 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2245 | } |
| 2246 | MCHBAR32(C2C3TT) = reg32; |
| 2247 | |
| 2248 | reg32 = MCHBAR32(C3C4TT); |
| 2249 | reg32 &= 0xffff0000; |
| 2250 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2251 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2252 | reg32 |= 0x0b80; |
| 2253 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2254 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2255 | reg32 |= 0x0980; |
| 2256 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2257 | } |
| 2258 | MCHBAR32(C3C4TT) = reg32; |
| 2259 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2260 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2261 | MCHBAR32(ECO) &= ~(1 << 16); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2262 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2263 | MCHBAR32(ECO) |= (1 << 16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2264 | |
| 2265 | #if 0 |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2266 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2267 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2268 | MCHBAR32(FSBPMC3) &= ~(1 << 29); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2269 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2270 | MCHBAR32(FSBPMC3) |= (1 << 29); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2271 | #endif |
| 2272 | MCHBAR32(FSBPMC3) &= ~(1 << 29); |
| 2273 | |
| 2274 | MCHBAR32(FSBPMC3) |= (1 << 21); |
| 2275 | |
| 2276 | MCHBAR32(FSBPMC3) &= ~(1 << 19); |
| 2277 | |
| 2278 | MCHBAR32(FSBPMC3) &= ~(1 << 13); |
| 2279 | |
| 2280 | reg32 = MCHBAR32(FSBPMC4); |
| 2281 | reg32 &= ~(3 << 24); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2282 | reg32 |= (2 << 24); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2283 | MCHBAR32(FSBPMC4) = reg32; |
| 2284 | |
| 2285 | MCHBAR32(FSBPMC4) |= (1 << 21); |
| 2286 | |
| 2287 | MCHBAR32(FSBPMC4) |= (1 << 5); |
| 2288 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2289 | if ((i945_silicon_revision() < 2)) { /* || cpuid() = 0x6e8 */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2290 | /* stepping 0 and 1 or CPUID 6e8 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2291 | MCHBAR32(FSBPMC4) &= ~(1 << 4); |
| 2292 | } else { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 2293 | MCHBAR32(FSBPMC4) |= (1 << 4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2294 | } |
| 2295 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2296 | reg8 = pci_read_config8(PCI_DEV(0, 0x0, 0), 0xfc); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2297 | reg8 |= (1 << 4); |
| 2298 | pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8); |
| 2299 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2300 | reg8 = pci_read_config8(PCI_DEV(0, 0x2, 0), 0xc1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2301 | reg8 |= (1 << 2); |
| 2302 | pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); |
| 2303 | |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 2304 | #ifdef C2_SELF_REFRESH_DISABLE |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2305 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2306 | if (integrated_graphics) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 2307 | printk(BIOS_DEBUG, "C2 self-refresh with IGD\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2308 | MCHBAR16(MIPMC4) = 0x0468; |
| 2309 | MCHBAR16(MIPMC5) = 0x046c; |
| 2310 | MCHBAR16(MIPMC6) = 0x046c; |
| 2311 | } else { |
| 2312 | MCHBAR16(MIPMC4) = 0x6468; |
| 2313 | MCHBAR16(MIPMC5) = 0x646c; |
| 2314 | MCHBAR16(MIPMC6) = 0x646c; |
| 2315 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2316 | #else |
| 2317 | if (integrated_graphics) { |
| 2318 | MCHBAR16(MIPMC4) = 0x04f8; |
| 2319 | MCHBAR16(MIPMC5) = 0x04fc; |
| 2320 | MCHBAR16(MIPMC6) = 0x04fc; |
| 2321 | } else { |
| 2322 | MCHBAR16(MIPMC4) = 0x64f8; |
| 2323 | MCHBAR16(MIPMC5) = 0x64fc; |
| 2324 | MCHBAR16(MIPMC6) = 0x64fc; |
| 2325 | } |
| 2326 | |
| 2327 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2328 | |
| 2329 | reg32 = MCHBAR32(PMCFG); |
| 2330 | reg32 &= ~(3 << 17); |
| 2331 | reg32 |= (2 << 17); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2332 | MCHBAR32(PMCFG) = reg32; |
| 2333 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2334 | MCHBAR32(PMCFG) |= (1 << 4); |
| 2335 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2336 | reg32 = MCHBAR32(0xc30); |
| 2337 | reg32 &= 0xffffff00; |
| 2338 | reg32 |= 0x01; |
| 2339 | MCHBAR32(0xc30) = reg32; |
| 2340 | |
| 2341 | MCHBAR32(0xb18) &= ~(1 << 21); |
| 2342 | } |
| 2343 | |
| 2344 | static void sdram_thermal_management(void) |
| 2345 | { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2346 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2347 | MCHBAR8(TCO1) = 0x00; |
| 2348 | MCHBAR8(TCO0) = 0x00; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2349 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2350 | /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr 0x30/0x32. */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2351 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 2352 | /* TODO This is not implemented yet. Volunteers? */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2353 | } |
| 2354 | |
| 2355 | static void sdram_save_receive_enable(void) |
| 2356 | { |
| 2357 | int i; |
| 2358 | u32 reg32; |
| 2359 | u8 values[4]; |
| 2360 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2361 | /* The following values are stored to an unused CMOS area and restored instead of |
| 2362 | * recalculated in case of an S3 resume. |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2363 | * |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2364 | * C0WL0REOST [7:0] -> 8 bit |
| 2365 | * C1WL0REOST [7:0] -> 8 bit |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2366 | * RCVENMT [11:8] [3:0] -> 8 bit |
| 2367 | * C0DRT1 [27:24] -> 4 bit |
| 2368 | * C1DRT1 [27:24] -> 4 bit |
| 2369 | */ |
| 2370 | |
| 2371 | values[0] = MCHBAR8(C0WL0REOST); |
| 2372 | values[1] = MCHBAR8(C1WL0REOST); |
| 2373 | |
| 2374 | reg32 = MCHBAR32(RCVENMT); |
| 2375 | values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f); |
| 2376 | |
| 2377 | reg32 = MCHBAR32(C0DRT1); |
| 2378 | values[3] = (reg32 >> 24) & 0x0f; |
| 2379 | reg32 = MCHBAR32(C1DRT1); |
| 2380 | values[3] |= (reg32 >> (24 - 4)) & 0xf0; |
| 2381 | |
| 2382 | /* coreboot only uses bytes 0 - 127 for its CMOS values so far |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 2383 | * so we grab bytes 128 - 131 to save the receive enable values |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2384 | */ |
| 2385 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 2386 | for (i = 0; i < 4; i++) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2387 | cmos_write(values[i], 128 + i); |
| 2388 | } |
| 2389 | |
| 2390 | static void sdram_recover_receive_enable(void) |
| 2391 | { |
| 2392 | int i; |
| 2393 | u32 reg32; |
| 2394 | u8 values[4]; |
| 2395 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 2396 | for (i = 0; i < 4; i++) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2397 | values[i] = cmos_read(128 + i); |
| 2398 | |
| 2399 | MCHBAR8(C0WL0REOST) = values[0]; |
| 2400 | MCHBAR8(C1WL0REOST) = values[1]; |
| 2401 | |
| 2402 | reg32 = MCHBAR32(RCVENMT); |
| 2403 | reg32 &= ~((0x0f << 8) | (0x0f << 0)); |
| 2404 | reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f); |
| 2405 | MCHBAR32(RCVENMT) = reg32; |
| 2406 | |
| 2407 | reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24); |
| 2408 | reg32 |= (u32)(values[3] & 0x0f) << 24; |
| 2409 | MCHBAR32(C0DRT1) = reg32; |
| 2410 | |
| 2411 | reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24); |
| 2412 | reg32 |= (u32)(values[3] & 0xf0) << (24 - 4); |
| 2413 | MCHBAR32(C1DRT1) = reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2414 | } |
| 2415 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2416 | static void sdram_program_receive_enable(struct sys_info *sysinfo) |
| 2417 | { |
| 2418 | MCHBAR32(REPC) |= (1 << 0); |
| 2419 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2420 | /* Program Receive Enable Timings */ |
| 2421 | if (sysinfo->boot_path == BOOT_PATH_RESUME) { |
| 2422 | sdram_recover_receive_enable(); |
| 2423 | } else { |
| 2424 | receive_enable_adjust(sysinfo); |
| 2425 | sdram_save_receive_enable(); |
| 2426 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2427 | |
| 2428 | MCHBAR32(C0DRC1) |= (1 << 6); |
| 2429 | MCHBAR32(C1DRC1) |= (1 << 6); |
| 2430 | MCHBAR32(C0DRC1) &= ~(1 << 6); |
| 2431 | MCHBAR32(C1DRC1) &= ~(1 << 6); |
| 2432 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2433 | MCHBAR32(MIPMC3) |= (0x0f << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2434 | } |
| 2435 | |
| 2436 | /** |
| 2437 | * @brief Enable On-Die Termination for DDR2. |
| 2438 | * |
| 2439 | */ |
| 2440 | |
| 2441 | static void sdram_on_die_termination(struct sys_info *sysinfo) |
| 2442 | { |
| 2443 | static const u32 odt[] = { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2444 | 0x00024911, 0xe0010000, |
| 2445 | 0x00049211, 0xe0020000, |
| 2446 | 0x0006db11, 0xe0030000, |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2447 | }; |
| 2448 | |
| 2449 | u32 reg32; |
| 2450 | int cas; |
| 2451 | |
| 2452 | reg32 = MCHBAR32(ODTC); |
| 2453 | reg32 &= ~(3 << 16); |
| 2454 | reg32 |= (1 << 14) | (1 << 6) | (2 << 16); |
| 2455 | MCHBAR32(ODTC) = reg32; |
| 2456 | |
Paul Menzel | b4d9f22 | 2020-03-14 10:34:29 +0100 | [diff] [blame] | 2457 | if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2458 | sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 2459 | printk(BIOS_DEBUG, "one dimm per channel config..\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2460 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2461 | reg32 = MCHBAR32(C0ODT); |
| 2462 | reg32 &= ~(7 << 28); |
| 2463 | MCHBAR32(C0ODT) = reg32; |
| 2464 | reg32 = MCHBAR32(C1ODT); |
| 2465 | reg32 &= ~(7 << 28); |
| 2466 | MCHBAR32(C1ODT) = reg32; |
| 2467 | } |
| 2468 | |
| 2469 | cas = sysinfo->cas; |
| 2470 | |
| 2471 | reg32 = MCHBAR32(C0ODT) & 0xfff00000; |
| 2472 | reg32 |= odt[(cas-3) * 2]; |
| 2473 | MCHBAR32(C0ODT) = reg32; |
| 2474 | |
| 2475 | reg32 = MCHBAR32(C1ODT) & 0xfff00000; |
| 2476 | reg32 |= odt[(cas-3) * 2]; |
| 2477 | MCHBAR32(C1ODT) = reg32; |
| 2478 | |
| 2479 | reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff; |
| 2480 | reg32 |= odt[((cas-3) * 2) + 1]; |
| 2481 | MCHBAR32(C0ODT + 4) = reg32; |
| 2482 | |
| 2483 | reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff; |
| 2484 | reg32 |= odt[((cas-3) * 2) + 1]; |
| 2485 | MCHBAR32(C1ODT + 4) = reg32; |
| 2486 | } |
| 2487 | |
| 2488 | /** |
| 2489 | * @brief Enable clocks to populated sockets |
| 2490 | */ |
| 2491 | |
| 2492 | static void sdram_enable_memory_clocks(struct sys_info *sysinfo) |
| 2493 | { |
| 2494 | u8 clocks[2] = { 0, 0 }; |
| 2495 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2496 | #if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 2497 | #define CLOCKS_WIDTH 2 |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2498 | #elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 2499 | #define CLOCKS_WIDTH 3 |
| 2500 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2501 | if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 2502 | clocks[0] |= (1 << CLOCKS_WIDTH)-1; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2503 | |
| 2504 | if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 2505 | clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2506 | |
| 2507 | if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 2508 | clocks[1] |= (1 << CLOCKS_WIDTH)-1; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2509 | |
| 2510 | if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 2511 | clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2512 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2513 | #if CONFIG(OVERRIDE_CLOCK_DISABLE) |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2514 | /* Usually system firmware turns off system memory clock signals to unused SO-DIMM slots |
| 2515 | * to reduce EMI and power consumption. |
| 2516 | * However, the Kontron 986LCD-M does not like unused clock signals to be disabled. |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2517 | */ |
| 2518 | |
| 2519 | clocks[0] = 0xf; /* force all clock gate pairs to enable */ |
| 2520 | clocks[1] = 0xf; /* force all clock gate pairs to enable */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2521 | #endif |
| 2522 | |
| 2523 | MCHBAR8(C0DCLKDIS) = clocks[0]; |
| 2524 | MCHBAR8(C1DCLKDIS) = clocks[1]; |
| 2525 | } |
| 2526 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2527 | #define RTT_ODT_NONE 0 |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 2528 | #define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2529 | #define RTT_ODT_75_OHM (1 << 5) |
| 2530 | #define RTT_ODT_150_OHM (1 << 9) |
| 2531 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2532 | #define EMRS_OCD_DEFAULT ((1 << 12) | (1 << 11) | (1 << 10)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2533 | |
| 2534 | #define MRS_CAS_3 (3 << 7) |
| 2535 | #define MRS_CAS_4 (4 << 7) |
| 2536 | #define MRS_CAS_5 (5 << 7) |
| 2537 | |
| 2538 | #define MRS_TWR_3 (2 << 12) |
| 2539 | #define MRS_TWR_4 (3 << 12) |
| 2540 | #define MRS_TWR_5 (4 << 12) |
| 2541 | |
| 2542 | #define MRS_BT (1 << 6) |
| 2543 | |
| 2544 | #define MRS_BL4 (2 << 3) |
| 2545 | #define MRS_BL8 (3 << 3) |
| 2546 | |
| 2547 | static void sdram_jedec_enable(struct sys_info *sysinfo) |
| 2548 | { |
| 2549 | int i, nonzero; |
| 2550 | u32 bankaddr = 0, tmpaddr, mrsaddr = 0; |
| 2551 | |
| 2552 | for (i = 0, nonzero = -1; i < 8; i++) { |
Elyes HAOUAS | 0191220 | 2019-01-19 16:36:38 +0100 | [diff] [blame] | 2553 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2554 | continue; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2555 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 2556 | printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i); |
Elyes HAOUAS | 0191220 | 2019-01-19 16:36:38 +0100 | [diff] [blame] | 2557 | |
| 2558 | if (nonzero != -1) { |
| 2559 | if (sysinfo->interleaved && nonzero < 4 && i >= 4) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2560 | bankaddr = 0x40; |
Elyes HAOUAS | 0191220 | 2019-01-19 16:36:38 +0100 | [diff] [blame] | 2561 | } else { |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 2562 | printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", |
| 2563 | nonzero); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2564 | bankaddr += sysinfo->banksize[nonzero] << |
| 2565 | (sysinfo->interleaved ? 26 : 25); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2566 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2567 | } |
| 2568 | |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 2569 | /* |
| 2570 | * We have a bank with a non-zero size... Remember it |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2571 | * for the next offset we have to calculate |
| 2572 | */ |
| 2573 | nonzero = i; |
| 2574 | |
| 2575 | /* Get CAS latency set up */ |
| 2576 | switch (sysinfo->cas) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2577 | case 5: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2578 | mrsaddr = MRS_CAS_5; |
| 2579 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2580 | case 4: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2581 | mrsaddr = MRS_CAS_4; |
| 2582 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2583 | case 3: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2584 | mrsaddr = MRS_CAS_3; |
| 2585 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2586 | default: |
| 2587 | die("Jedec Error (CAS).\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2588 | } |
| 2589 | |
| 2590 | /* Get tWR set */ |
| 2591 | switch (sysinfo->twr) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2592 | case 5: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2593 | mrsaddr |= MRS_TWR_5; |
| 2594 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2595 | case 4: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2596 | mrsaddr |= MRS_TWR_4; |
| 2597 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2598 | case 3: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2599 | mrsaddr |= MRS_TWR_3; |
| 2600 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2601 | default: |
| 2602 | die("Jedec Error (tWR).\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2603 | } |
| 2604 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2605 | /* Set "Burst Type" */ |
| 2606 | mrsaddr |= MRS_BT; |
| 2607 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2608 | /* Interleaved */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2609 | if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2610 | mrsaddr = mrsaddr << 1; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2611 | |
| 2612 | /* Only burst length 8 supported */ |
| 2613 | mrsaddr |= MRS_BL8; |
| 2614 | |
| 2615 | /* Apply NOP */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2616 | PRINTK_DEBUG("Apply NOP\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2617 | do_ram_command(RAM_COMMAND_NOP); |
| 2618 | ram_read32(bankaddr); |
| 2619 | |
| 2620 | /* Precharge all banks */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2621 | PRINTK_DEBUG("All Banks Precharge\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2622 | do_ram_command(RAM_COMMAND_PRECHARGE); |
| 2623 | ram_read32(bankaddr); |
| 2624 | |
| 2625 | /* Extended Mode Register Set (2) */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2626 | PRINTK_DEBUG("Extended Mode Register Set(2)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2627 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2); |
| 2628 | ram_read32(bankaddr); |
| 2629 | |
| 2630 | /* Extended Mode Register Set (3) */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2631 | PRINTK_DEBUG("Extended Mode Register Set(3)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2632 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3); |
| 2633 | ram_read32(bankaddr); |
| 2634 | |
| 2635 | /* Extended Mode Register Set */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2636 | PRINTK_DEBUG("Extended Mode Register Set\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2637 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); |
| 2638 | tmpaddr = bankaddr; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2639 | if (!sdram_capabilities_dual_channel()) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2640 | tmpaddr |= RTT_ODT_75_OHM; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2641 | else if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2642 | tmpaddr |= (RTT_ODT_150_OHM << 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2643 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2644 | tmpaddr |= RTT_ODT_150_OHM; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2645 | ram_read32(tmpaddr); |
| 2646 | |
| 2647 | /* Mode Register Set: Reset DLLs */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2648 | PRINTK_DEBUG("MRS: Reset DLLs\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2649 | do_ram_command(RAM_COMMAND_MRS); |
| 2650 | tmpaddr = bankaddr; |
| 2651 | tmpaddr |= mrsaddr; |
| 2652 | /* Set DLL reset bit */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2653 | if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2654 | tmpaddr |= (1 << 12); |
| 2655 | else |
| 2656 | tmpaddr |= (1 << 11); |
| 2657 | ram_read32(tmpaddr); |
| 2658 | |
| 2659 | /* Precharge all banks */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2660 | PRINTK_DEBUG("All Banks Precharge\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2661 | do_ram_command(RAM_COMMAND_PRECHARGE); |
| 2662 | ram_read32(bankaddr); |
| 2663 | |
| 2664 | /* CAS before RAS Refresh */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2665 | PRINTK_DEBUG("CAS before RAS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2666 | do_ram_command(RAM_COMMAND_CBR); |
| 2667 | |
| 2668 | /* CBR wants two READs */ |
| 2669 | ram_read32(bankaddr); |
| 2670 | ram_read32(bankaddr); |
| 2671 | |
| 2672 | /* Mode Register Set: Enable DLLs */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2673 | PRINTK_DEBUG("MRS: Enable DLLs\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2674 | do_ram_command(RAM_COMMAND_MRS); |
| 2675 | |
| 2676 | tmpaddr = bankaddr; |
| 2677 | tmpaddr |= mrsaddr; |
| 2678 | ram_read32(tmpaddr); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2679 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2680 | /* Extended Mode Register Set */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2681 | PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2682 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2683 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2684 | tmpaddr = bankaddr; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2685 | if (!sdram_capabilities_dual_channel()) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2686 | tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2687 | else if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2688 | tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2689 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2690 | tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2691 | ram_read32(tmpaddr); |
| 2692 | |
| 2693 | /* Extended Mode Register Set */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2694 | PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2695 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); |
| 2696 | |
| 2697 | tmpaddr = bankaddr; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2698 | if (!sdram_capabilities_dual_channel()) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2699 | tmpaddr |= RTT_ODT_75_OHM; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2700 | else if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2701 | tmpaddr |= (RTT_ODT_150_OHM << 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2702 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2703 | tmpaddr |= RTT_ODT_150_OHM; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2704 | ram_read32(tmpaddr); |
| 2705 | } |
| 2706 | } |
| 2707 | |
| 2708 | static void sdram_init_complete(void) |
| 2709 | { |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2710 | PRINTK_DEBUG("Normal Operation\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2711 | do_ram_command(RAM_COMMAND_NORMAL); |
| 2712 | } |
| 2713 | |
| 2714 | static void sdram_setup_processor_side(void) |
| 2715 | { |
| 2716 | if (i945_silicon_revision() == 0) |
| 2717 | MCHBAR32(FSBPMC3) |= (1 << 2); |
| 2718 | |
| 2719 | MCHBAR8(0xb00) |= 1; |
| 2720 | |
| 2721 | if (i945_silicon_revision() == 0) |
| 2722 | MCHBAR32(SLPCTL) |= (1 << 8); |
| 2723 | } |
| 2724 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2725 | /** |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2726 | * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 |
Martin Roth | f4cb412 | 2015-01-06 10:27:39 -0700 | [diff] [blame] | 2727 | * @param spd_addresses pointer to a list of SPD addresses |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2728 | */ |
Sven Schnelle | 541269b | 2011-02-21 09:39:17 +0000 | [diff] [blame] | 2729 | void sdram_initialize(int boot_path, const u8 *spd_addresses) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2730 | { |
| 2731 | struct sys_info sysinfo; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 2732 | u8 reg8; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2733 | |
Patrick Georgi | 771328f | 2015-07-13 19:24:07 +0200 | [diff] [blame] | 2734 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 2735 | printk(BIOS_DEBUG, "Setting up RAM controller.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2736 | |
| 2737 | memset(&sysinfo, 0, sizeof(sysinfo)); |
| 2738 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2739 | sysinfo.boot_path = boot_path; |
Sven Schnelle | 541269b | 2011-02-21 09:39:17 +0000 | [diff] [blame] | 2740 | sysinfo.spd_addresses = spd_addresses; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2741 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2742 | /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */ |
| 2743 | sdram_get_dram_configuration(&sysinfo); |
| 2744 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 2745 | /* If error, do cold boot */ |
| 2746 | sdram_detect_errors(&sysinfo); |
| 2747 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2748 | /* Program PLL settings */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2749 | sdram_program_pll_settings(&sysinfo); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2750 | |
Arthur Heymans | 1853781 | 2016-12-28 21:20:45 +0100 | [diff] [blame] | 2751 | /* |
| 2752 | * Program Graphics Frequency |
| 2753 | * Set core display and render clock on 945GC to the max |
| 2754 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2755 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Arthur Heymans | 1853781 | 2016-12-28 21:20:45 +0100 | [diff] [blame] | 2756 | sdram_program_graphics_frequency(&sysinfo); |
| 2757 | else |
| 2758 | pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2759 | |
| 2760 | /* Program System Memory Frequency */ |
| 2761 | sdram_program_memory_frequency(&sysinfo); |
| 2762 | |
| 2763 | /* Determine Mode of Operation (Interleaved etc) */ |
| 2764 | sdram_set_channel_mode(&sysinfo); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2765 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2766 | /* Program Clock Crossing values */ |
| 2767 | sdram_program_clock_crossing(); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2768 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2769 | /* Disable fast dispatch */ |
| 2770 | sdram_disable_fast_dispatch(); |
| 2771 | |
| 2772 | /* Enable WIODLL Power Down in ACPI states */ |
| 2773 | MCHBAR32(C0DMC) |= (1 << 24); |
| 2774 | MCHBAR32(C1DMC) |= (1 << 24); |
| 2775 | |
| 2776 | /* Program DRAM Row Boundary/Attribute Registers */ |
| 2777 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2778 | /* program row size DRB and set TOLUD */ |
| 2779 | sdram_program_row_boundaries(&sysinfo); |
| 2780 | |
| 2781 | /* program page size DRA */ |
| 2782 | sdram_set_row_attributes(&sysinfo); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2783 | |
| 2784 | /* Program CxBNKARC */ |
| 2785 | sdram_set_bank_architecture(&sysinfo); |
| 2786 | |
| 2787 | /* Program DRAM Timing and Control registers based on SPD */ |
| 2788 | sdram_set_timing_and_control(&sysinfo); |
| 2789 | |
| 2790 | /* On-Die Termination Adjustment */ |
| 2791 | sdram_on_die_termination(&sysinfo); |
| 2792 | |
| 2793 | /* Pre Jedec Initialization */ |
| 2794 | sdram_pre_jedec_initialization(); |
| 2795 | |
| 2796 | /* Perform System Memory IO Initialization */ |
| 2797 | sdram_initialize_system_memory_io(&sysinfo); |
| 2798 | |
| 2799 | /* Perform System Memory IO Buffer Enable */ |
| 2800 | sdram_enable_system_memory_io(&sysinfo); |
| 2801 | |
| 2802 | /* Enable System Memory Clocks */ |
| 2803 | sdram_enable_memory_clocks(&sysinfo); |
| 2804 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2805 | if (boot_path == BOOT_PATH_NORMAL) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2806 | /* Jedec Initialization sequence */ |
| 2807 | sdram_jedec_enable(&sysinfo); |
| 2808 | } |
| 2809 | |
| 2810 | /* Program Power Management Registers */ |
| 2811 | sdram_power_management(&sysinfo); |
| 2812 | |
| 2813 | /* Post Jedec Init */ |
| 2814 | sdram_post_jedec_initialization(&sysinfo); |
| 2815 | |
| 2816 | /* Program DRAM Throttling */ |
| 2817 | sdram_thermal_management(); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2818 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2819 | /* Normal Operations */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 2820 | sdram_init_complete(); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2821 | |
| 2822 | /* Program Receive Enable Timings */ |
| 2823 | sdram_program_receive_enable(&sysinfo); |
| 2824 | |
| 2825 | /* Enable Periodic RCOMP */ |
| 2826 | sdram_enable_rcomp(); |
| 2827 | |
| 2828 | /* Tell ICH7 that we're done */ |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 2829 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2830 | reg8 &= ~(1 << 7); |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 2831 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2832 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 2833 | printk(BIOS_DEBUG, "RAM initialization finished.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2834 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2835 | sdram_setup_processor_side(); |
Patrick Georgi | 771328f | 2015-07-13 19:24:07 +0200 | [diff] [blame] | 2836 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2837 | } |