Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 3 | #include <arch/hlt.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 4 | #include <arch/io.h> |
| 5 | #include <console/console.h> |
| 6 | #include <cpu/x86/cache.h> |
| 7 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | e31ec29 | 2019-08-10 17:27:01 +0300 | [diff] [blame] | 8 | #include <cpu/intel/em64t100_save_state.h> |
Dinesh Gehlot | ba09eb7 | 2023-01-17 05:06:10 +0000 | [diff] [blame] | 9 | #include <device/mmio.h> |
| 10 | #include <device/pci_ops.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 11 | #include <device/pci_def.h> |
| 12 | #include <elog.h> |
Dinesh Gehlot | ba09eb7 | 2023-01-17 05:06:10 +0000 | [diff] [blame] | 13 | #include <gpio.h> |
Kyösti Mälkki | 85556ac | 2023-05-02 12:53:00 +0300 | [diff] [blame] | 14 | #include <smmstore.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | #include <soc/nvs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/pm.h> |
| 18 | #include <spi-generic.h> |
| 19 | #include <stdint.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | void southbridge_smi_set_eos(void) |
| 22 | { |
| 23 | enable_smi(EOS); |
| 24 | } |
| 25 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 26 | static void busmaster_disable_on_bus(int bus) |
| 27 | { |
| 28 | int slot, func; |
| 29 | unsigned int val; |
| 30 | unsigned char hdr; |
| 31 | |
| 32 | for (slot = 0; slot < 0x20; slot++) { |
| 33 | for (func = 0; func < 8; func++) { |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 34 | u16 reg16; |
Elyes HAOUAS | c8a649c | 2018-06-10 23:36:44 +0200 | [diff] [blame] | 35 | pci_devfn_t dev = PCI_DEV(bus, slot, func); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 36 | |
| 37 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
| 38 | |
| 39 | if (val == 0xffffffff || val == 0x00000000 || |
| 40 | val == 0x0000ffff || val == 0xffff0000) |
| 41 | continue; |
| 42 | |
| 43 | /* Disable Bus Mastering for this one device */ |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 44 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 45 | reg16 &= ~PCI_COMMAND_MASTER; |
| 46 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 47 | |
| 48 | /* If this is a bridge, then follow it. */ |
| 49 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 50 | hdr &= 0x7f; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 51 | if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 52 | unsigned int buses; |
| 53 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 54 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 55 | } |
| 56 | } |
| 57 | } |
| 58 | } |
| 59 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 60 | static void tristate_gpios(uint32_t val) |
| 61 | { |
| 62 | /* Tri-state eMMC */ |
Elyes Haouas | a506451 | 2023-09-17 10:22:02 +0200 | [diff] [blame] | 63 | write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_CMD_MMIO_OFFSET, val); |
| 64 | write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D0_MMIO_OFFSET, val); |
| 65 | write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D1_MMIO_OFFSET, val); |
| 66 | write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D2_MMIO_OFFSET, val); |
| 67 | write32p(COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D3_MMIO_OFFSET, val); |
| 68 | write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_D4_SD_WE_MMIO_OFFSET, val); |
| 69 | write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_D5_MMIO_OFFSET, val); |
| 70 | write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_D6_MMIO_OFFSET, val); |
| 71 | write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val); |
| 72 | write32p(COMMUNITY_GPSOUTHEAST_BASE + MMC1_RCLK_OFFSET, val); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 73 | |
| 74 | /* Tri-state HDMI */ |
Elyes Haouas | a506451 | 2023-09-17 10:22:02 +0200 | [diff] [blame] | 75 | write32p(COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SDA_MMIO_OFFSET, val); |
| 76 | write32p(COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val); |
Ravi Sarawadi | a5d9888 | 2015-08-11 14:06:15 -0700 | [diff] [blame] | 77 | |
| 78 | /* Tri-state CFIO 139 and 140 */ |
Elyes Haouas | a506451 | 2023-09-17 10:22:02 +0200 | [diff] [blame] | 79 | write32p(COMMUNITY_GPSOUTHWEST_BASE + CFIO_139_MMIO_OFFSET, val); |
| 80 | write32p(COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 81 | } |
| 82 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 83 | static void southbridge_smi_sleep(void) |
| 84 | { |
| 85 | uint32_t reg32; |
| 86 | uint8_t slp_typ; |
| 87 | uint16_t pmbase = get_pmbase(); |
| 88 | |
| 89 | /* First, disable further SMIs */ |
| 90 | disable_smi(SLP_SMI_EN); |
| 91 | |
| 92 | /* Figure out SLP_TYP */ |
| 93 | reg32 = inl(pmbase + PM1_CNT); |
| 94 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 95 | slp_typ = acpi_sleep_from_pm1(reg32); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 96 | |
| 97 | /* Do any mainboard sleep handling */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 98 | mainboard_smi_sleep(slp_typ); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 99 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 100 | /* Log S3, S4, and S5 entry */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 101 | if (slp_typ >= ACPI_S3) |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 102 | elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); |
| 103 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 104 | /* Clear pending GPE events */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 105 | clear_gpe_status(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 106 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 107 | /* Next, do the deed. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 108 | switch (slp_typ) { |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 109 | case ACPI_S0: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 110 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 111 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 112 | case ACPI_S1: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 113 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 114 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 115 | case ACPI_S3: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 116 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 117 | |
| 118 | /* Invalidate the cache before going to S3 */ |
| 119 | wbinvd(); |
| 120 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 121 | case ACPI_S4: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 122 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 123 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 124 | case ACPI_S5: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 125 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 126 | |
| 127 | /* Disable all GPE */ |
| 128 | disable_all_gpe(); |
| 129 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 130 | /* Also iterates over all bridges on bus 0 */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 131 | busmaster_disable_on_bus(0); |
| 132 | break; |
| 133 | default: |
| 134 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 135 | break; |
| 136 | } |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 137 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 138 | /* Clear pending wake status bit to avoid immediate wake */ |
Elyes Haouas | a506451 | 2023-09-17 10:22:02 +0200 | [diff] [blame] | 139 | write32p(0xfed88000 + 0x0200, read32p(0xfed88000 + 0x0200)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 140 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 141 | /* Tri-state specific GPIOS to avoid leakage during S3/S5 */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 142 | if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 143 | tristate_gpios(PAD_CONTROL_REG0_TRISTATE); |
| 144 | |
| 145 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 146 | * Write back to the SLP register to cause the originally intended event again. |
| 147 | * We need to set BIT13 (SLP_EN) though to make the sleep happen. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 148 | */ |
| 149 | enable_pm1_control(SLP_EN); |
| 150 | |
| 151 | /* Make sure to stop executing code here for S3/S4/S5 */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 152 | if (slp_typ >= ACPI_S3) |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 153 | hlt(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 154 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 155 | /* |
| 156 | * In most sleep states, the code flow of this function ends at |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 157 | * the line above. However, if we entered sleep state S1 and wake |
| 158 | * up again, we will continue to execute code in this function. |
| 159 | */ |
| 160 | reg32 = inl(pmbase + PM1_CNT); |
| 161 | if (reg32 & SCI_EN) { |
| 162 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 163 | disable_pm1_control(SLP_EN | SLP_TYP); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 168 | * Look for Synchronous IO SMI and use save state from that core in case |
| 169 | * we are not running on the same core that initiated the IO transaction. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 170 | */ |
| 171 | static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) |
| 172 | { |
| 173 | em64t100_smm_state_save_area_t *state; |
| 174 | int node; |
| 175 | |
| 176 | /* Check all nodes looking for the one that issued the IO */ |
| 177 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
| 178 | state = smm_get_save_state(node); |
| 179 | |
| 180 | /* Check for Synchronous IO (bit0==1) */ |
| 181 | if (!(state->io_misc_info & (1 << 0))) |
| 182 | continue; |
| 183 | |
| 184 | /* Make sure it was a write (bit4==0) */ |
| 185 | if (state->io_misc_info & (1 << 4)) |
| 186 | continue; |
| 187 | |
| 188 | /* Check for APMC IO port */ |
| 189 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 190 | continue; |
| 191 | |
| 192 | /* Check AX against the requested command */ |
| 193 | if ((state->rax & 0xff) != cmd) |
| 194 | continue; |
| 195 | |
| 196 | return state; |
| 197 | } |
| 198 | |
| 199 | return NULL; |
| 200 | } |
| 201 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 202 | static void southbridge_smi_gsmi(void) |
| 203 | { |
| 204 | u32 *ret, *param; |
| 205 | uint8_t sub_command; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 206 | em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 207 | |
| 208 | if (!io_smi) |
| 209 | return; |
| 210 | |
| 211 | /* Command and return value in EAX */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 212 | ret = (u32 *)&io_smi->rax; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 213 | sub_command = (uint8_t)(*ret >> 8); |
| 214 | |
| 215 | /* Parameter buffer in EBX */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 216 | param = (u32 *)&io_smi->rbx; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 217 | |
| 218 | /* drivers/elog/gsmi.c */ |
| 219 | *ret = gsmi_exec(sub_command, param); |
| 220 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 221 | |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 222 | static void southbridge_smi_store(void) |
| 223 | { |
| 224 | u8 sub_command, ret; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 225 | em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 226 | uint32_t reg_ebx; |
| 227 | |
| 228 | if (!io_smi) |
| 229 | return; |
| 230 | /* Command and return value in EAX */ |
| 231 | sub_command = (io_smi->rax >> 8) & 0xff; |
| 232 | |
| 233 | /* Parameter buffer in EBX */ |
| 234 | reg_ebx = io_smi->rbx; |
| 235 | |
| 236 | /* drivers/smmstore/smi.c */ |
| 237 | ret = smmstore_exec(sub_command, (void *)reg_ebx); |
| 238 | io_smi->rax = ret; |
| 239 | } |
| 240 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 241 | static void southbridge_smi_apmc(void) |
| 242 | { |
| 243 | uint8_t reg8; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 244 | |
Kyösti Mälkki | 9a1620f | 2021-01-08 13:27:33 +0200 | [diff] [blame] | 245 | reg8 = apm_get_apmc(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 246 | switch (reg8) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 247 | case APM_CNT_ACPI_DISABLE: |
| 248 | disable_pm1_control(SCI_EN); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 249 | break; |
| 250 | case APM_CNT_ACPI_ENABLE: |
| 251 | enable_pm1_control(SCI_EN); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 252 | break; |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 253 | case APM_CNT_ELOG_GSMI: |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 254 | if (CONFIG(ELOG_GSMI)) |
| 255 | southbridge_smi_gsmi(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 256 | break; |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 257 | case APM_CNT_SMMSTORE: |
| 258 | if (CONFIG(SMMSTORE)) |
| 259 | southbridge_smi_store(); |
| 260 | break; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | mainboard_smi_apmc(reg8); |
| 264 | } |
| 265 | |
| 266 | static void southbridge_smi_pm1(void) |
| 267 | { |
| 268 | uint16_t pm1_sts = clear_pm1_status(); |
| 269 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 270 | /* While OSPM is not active, poweroff immediately on a power button event */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 271 | if (pm1_sts & PWRBTN_STS) { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 272 | /* Power button pressed */ |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 273 | elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 274 | disable_pm1_control(-1UL); |
| 275 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | static void southbridge_smi_gpe0(void) |
| 280 | { |
| 281 | clear_gpe_status(); |
| 282 | } |
| 283 | |
| 284 | static void southbridge_smi_tco(void) |
| 285 | { |
| 286 | uint32_t tco_sts = clear_tco_status(); |
| 287 | |
| 288 | /* Any TCO event? */ |
| 289 | if (!tco_sts) |
| 290 | return; |
| 291 | |
| 292 | if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ |
| 293 | /* Handle TCO timeout */ |
| 294 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | static void southbridge_smi_periodic(void) |
| 299 | { |
| 300 | uint32_t reg32; |
| 301 | |
| 302 | reg32 = inl(get_pmbase() + SMI_EN); |
| 303 | |
| 304 | /* Are periodic SMIs enabled? */ |
| 305 | if ((reg32 & PERIODIC_EN) == 0) |
| 306 | return; |
| 307 | |
| 308 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 309 | } |
| 310 | |
| 311 | typedef void (*smi_handler_t)(void); |
| 312 | |
| 313 | static const smi_handler_t southbridge_smi[32] = { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 314 | NULL, /* [0] reserved */ |
| 315 | NULL, /* [1] reserved */ |
| 316 | NULL, /* [2] BIOS_STS */ |
| 317 | NULL, /* [3] LEGACY_USB_STS */ |
| 318 | southbridge_smi_sleep, /* [4] SLP_SMI_STS */ |
| 319 | southbridge_smi_apmc, /* [5] APM_STS */ |
| 320 | NULL, /* [6] SWSMI_TMR_STS */ |
| 321 | NULL, /* [7] reserved */ |
| 322 | southbridge_smi_pm1, /* [8] PM1_STS */ |
| 323 | southbridge_smi_gpe0, /* [9] GPE0_STS */ |
| 324 | NULL, /* [10] reserved */ |
| 325 | NULL, /* [11] reserved */ |
| 326 | NULL, /* [12] reserved */ |
| 327 | southbridge_smi_tco, /* [13] TCO_STS */ |
| 328 | southbridge_smi_periodic, /* [14] PERIODIC_STS */ |
| 329 | NULL, /* [15] SERIRQ_SMI_STS */ |
| 330 | NULL, /* [16] SMBUS_SMI_STS */ |
| 331 | NULL, /* [17] LEGACY_USB2_STS */ |
| 332 | NULL, /* [18] INTEL_USB2_STS */ |
| 333 | NULL, /* [19] reserved */ |
| 334 | NULL, /* [20] PCI_EXP_SMI_STS */ |
| 335 | NULL, /* [21] reserved */ |
| 336 | NULL, /* [22] reserved */ |
| 337 | NULL, /* [23] reserved */ |
| 338 | NULL, /* [24] reserved */ |
| 339 | NULL, /* [25] reserved */ |
| 340 | NULL, /* [26] SPI_STS */ |
| 341 | NULL, /* [27] reserved */ |
| 342 | NULL, /* [28] PUNIT */ |
| 343 | NULL, /* [29] GUNIT */ |
| 344 | NULL, /* [30] reserved */ |
| 345 | NULL /* [31] reserved */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 346 | }; |
| 347 | |
| 348 | void southbridge_smi_handler(void) |
| 349 | { |
| 350 | int i; |
| 351 | uint32_t smi_sts; |
| 352 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 353 | /* |
| 354 | * We need to clear the SMI status registers, or we won't see what's |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 355 | * happening in the following calls. |
| 356 | */ |
| 357 | smi_sts = clear_smi_status(); |
| 358 | |
| 359 | /* Call SMI sub handler for each of the status bits */ |
| 360 | for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { |
| 361 | if (!(smi_sts & (1 << i))) |
| 362 | continue; |
| 363 | |
| 364 | if (southbridge_smi[i] != NULL) { |
| 365 | southbridge_smi[i](); |
| 366 | } else { |
| 367 | printk(BIOS_DEBUG, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 368 | "SMI_STS[%d] occurred, but no handler available.\n", i); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 369 | } |
| 370 | } |
| 371 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 372 | /* |
| 373 | * The GPIO SMI events do not have a status bit in SMI_STS. Therefore, |
| 374 | * these events need to be cleared and checked unconditionally. |
| 375 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 376 | mainboard_smi_gpi(clear_alt_status()); |
| 377 | } |