Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 3 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 4 | #include <arch/hlt.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 5 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 8 | #include <console/console.h> |
| 9 | #include <cpu/x86/cache.h> |
| 10 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | e31ec29 | 2019-08-10 17:27:01 +0300 | [diff] [blame] | 11 | #include <cpu/intel/em64t100_save_state.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 12 | #include <device/pci_def.h> |
| 13 | #include <elog.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 14 | #include <soc/nvs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pm.h> |
| 17 | #include <spi-generic.h> |
| 18 | #include <stdint.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 19 | #include <soc/gpio.h> |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 20 | #include <smmstore.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | |
| 22 | /* GNVS needs to be set by coreboot initiating a software SMI. */ |
| 23 | static global_nvs_t *gnvs; |
| 24 | static int smm_initialized; |
| 25 | |
| 26 | int southbridge_io_trap_handler(int smif) |
| 27 | { |
| 28 | switch (smif) { |
| 29 | case 0x32: |
| 30 | printk(BIOS_DEBUG, "OS Init\n"); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 31 | /* |
| 32 | * gnvs->smif: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | * On success, the IO Trap Handler returns 0 |
| 34 | * On failure, the IO Trap Handler returns a value != 0 |
| 35 | */ |
| 36 | gnvs->smif = 0; |
| 37 | return 1; /* IO trap handled */ |
| 38 | } |
| 39 | |
| 40 | /* Not handled */ |
| 41 | return 0; |
| 42 | } |
| 43 | |
| 44 | void southbridge_smi_set_eos(void) |
| 45 | { |
| 46 | enable_smi(EOS); |
| 47 | } |
| 48 | |
| 49 | global_nvs_t *smm_get_gnvs(void) |
| 50 | { |
| 51 | return gnvs; |
| 52 | } |
| 53 | |
| 54 | static void busmaster_disable_on_bus(int bus) |
| 55 | { |
| 56 | int slot, func; |
| 57 | unsigned int val; |
| 58 | unsigned char hdr; |
| 59 | |
| 60 | for (slot = 0; slot < 0x20; slot++) { |
| 61 | for (func = 0; func < 8; func++) { |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame^] | 62 | u16 reg16; |
Elyes HAOUAS | c8a649c | 2018-06-10 23:36:44 +0200 | [diff] [blame] | 63 | pci_devfn_t dev = PCI_DEV(bus, slot, func); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 64 | |
| 65 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
| 66 | |
| 67 | if (val == 0xffffffff || val == 0x00000000 || |
| 68 | val == 0x0000ffff || val == 0xffff0000) |
| 69 | continue; |
| 70 | |
| 71 | /* Disable Bus Mastering for this one device */ |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame^] | 72 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 73 | reg16 &= ~PCI_COMMAND_MASTER; |
| 74 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 75 | |
| 76 | /* If this is a bridge, then follow it. */ |
| 77 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 78 | hdr &= 0x7f; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 79 | if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 80 | unsigned int buses; |
| 81 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 82 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 83 | } |
| 84 | } |
| 85 | } |
| 86 | } |
| 87 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 88 | static void tristate_gpios(uint32_t val) |
| 89 | { |
| 90 | /* Tri-state eMMC */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 91 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_CMD_MMIO_OFFSET, val); |
| 92 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D0_MMIO_OFFSET, val); |
| 93 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D1_MMIO_OFFSET, val); |
| 94 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D2_MMIO_OFFSET, val); |
| 95 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D3_MMIO_OFFSET, val); |
| 96 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D4_SD_WE_MMIO_OFFSET, val); |
| 97 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D5_MMIO_OFFSET, val); |
| 98 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D6_MMIO_OFFSET, val); |
| 99 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val); |
| 100 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_RCLK_OFFSET, val); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 101 | |
| 102 | /* Tri-state HDMI */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 103 | write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SDA_MMIO_OFFSET, val); |
| 104 | write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val); |
Ravi Sarawadi | a5d9888 | 2015-08-11 14:06:15 -0700 | [diff] [blame] | 105 | |
| 106 | /* Tri-state CFIO 139 and 140 */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 107 | write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_139_MMIO_OFFSET, val); |
| 108 | write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 112 | static void southbridge_smi_sleep(void) |
| 113 | { |
| 114 | uint32_t reg32; |
| 115 | uint8_t slp_typ; |
| 116 | uint16_t pmbase = get_pmbase(); |
| 117 | |
| 118 | /* First, disable further SMIs */ |
| 119 | disable_smi(SLP_SMI_EN); |
| 120 | |
| 121 | /* Figure out SLP_TYP */ |
| 122 | reg32 = inl(pmbase + PM1_CNT); |
| 123 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 124 | slp_typ = acpi_sleep_from_pm1(reg32); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 125 | |
| 126 | /* Do any mainboard sleep handling */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 127 | mainboard_smi_sleep(slp_typ); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 128 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 129 | /* Log S3, S4, and S5 entry */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 130 | if (slp_typ >= ACPI_S3) |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 131 | elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); |
| 132 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 133 | /* Clear pending GPE events */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 134 | clear_gpe_status(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 135 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 136 | /* Next, do the deed. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 137 | switch (slp_typ) { |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 138 | case ACPI_S0: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 139 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 140 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 141 | case ACPI_S1: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 142 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 143 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 144 | case ACPI_S3: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 145 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 146 | |
| 147 | /* Invalidate the cache before going to S3 */ |
| 148 | wbinvd(); |
| 149 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 150 | case ACPI_S4: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 151 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 152 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 153 | case ACPI_S5: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 154 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 155 | |
| 156 | /* Disable all GPE */ |
| 157 | disable_all_gpe(); |
| 158 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 159 | /* Also iterates over all bridges on bus 0 */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 160 | busmaster_disable_on_bus(0); |
| 161 | break; |
| 162 | default: |
| 163 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 164 | break; |
| 165 | } |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 166 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 167 | /* Clear pending wake status bit to avoid immediate wake */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 168 | write32((void *)(0xfed88000 + 0x0200), read32((void *)(0xfed88000 + 0x0200))); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 169 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 170 | /* Tri-state specific GPIOS to avoid leakage during S3/S5 */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 171 | if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 172 | tristate_gpios(PAD_CONTROL_REG0_TRISTATE); |
| 173 | |
| 174 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 175 | * Write back to the SLP register to cause the originally intended event again. |
| 176 | * We need to set BIT13 (SLP_EN) though to make the sleep happen. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 177 | */ |
| 178 | enable_pm1_control(SLP_EN); |
| 179 | |
| 180 | /* Make sure to stop executing code here for S3/S4/S5 */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 181 | if (slp_typ >= ACPI_S3) |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 182 | hlt(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 183 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 184 | /* |
| 185 | * In most sleep states, the code flow of this function ends at |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 186 | * the line above. However, if we entered sleep state S1 and wake |
| 187 | * up again, we will continue to execute code in this function. |
| 188 | */ |
| 189 | reg32 = inl(pmbase + PM1_CNT); |
| 190 | if (reg32 & SCI_EN) { |
| 191 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 192 | disable_pm1_control(SLP_EN | SLP_TYP); |
| 193 | } |
| 194 | } |
| 195 | |
| 196 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 197 | * Look for Synchronous IO SMI and use save state from that core in case |
| 198 | * we are not running on the same core that initiated the IO transaction. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 199 | */ |
| 200 | static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) |
| 201 | { |
| 202 | em64t100_smm_state_save_area_t *state; |
| 203 | int node; |
| 204 | |
| 205 | /* Check all nodes looking for the one that issued the IO */ |
| 206 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
| 207 | state = smm_get_save_state(node); |
| 208 | |
| 209 | /* Check for Synchronous IO (bit0==1) */ |
| 210 | if (!(state->io_misc_info & (1 << 0))) |
| 211 | continue; |
| 212 | |
| 213 | /* Make sure it was a write (bit4==0) */ |
| 214 | if (state->io_misc_info & (1 << 4)) |
| 215 | continue; |
| 216 | |
| 217 | /* Check for APMC IO port */ |
| 218 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 219 | continue; |
| 220 | |
| 221 | /* Check AX against the requested command */ |
| 222 | if ((state->rax & 0xff) != cmd) |
| 223 | continue; |
| 224 | |
| 225 | return state; |
| 226 | } |
| 227 | |
| 228 | return NULL; |
| 229 | } |
| 230 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 231 | static void southbridge_smi_gsmi(void) |
| 232 | { |
| 233 | u32 *ret, *param; |
| 234 | uint8_t sub_command; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 235 | em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 236 | |
| 237 | if (!io_smi) |
| 238 | return; |
| 239 | |
| 240 | /* Command and return value in EAX */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 241 | ret = (u32 *)&io_smi->rax; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 242 | sub_command = (uint8_t)(*ret >> 8); |
| 243 | |
| 244 | /* Parameter buffer in EBX */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 245 | param = (u32 *)&io_smi->rbx; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 246 | |
| 247 | /* drivers/elog/gsmi.c */ |
| 248 | *ret = gsmi_exec(sub_command, param); |
| 249 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 250 | |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 251 | static void southbridge_smi_store(void) |
| 252 | { |
| 253 | u8 sub_command, ret; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 254 | em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 255 | uint32_t reg_ebx; |
| 256 | |
| 257 | if (!io_smi) |
| 258 | return; |
| 259 | /* Command and return value in EAX */ |
| 260 | sub_command = (io_smi->rax >> 8) & 0xff; |
| 261 | |
| 262 | /* Parameter buffer in EBX */ |
| 263 | reg_ebx = io_smi->rbx; |
| 264 | |
| 265 | /* drivers/smmstore/smi.c */ |
| 266 | ret = smmstore_exec(sub_command, (void *)reg_ebx); |
| 267 | io_smi->rax = ret; |
| 268 | } |
| 269 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 270 | static void southbridge_smi_apmc(void) |
| 271 | { |
| 272 | uint8_t reg8; |
| 273 | em64t100_smm_state_save_area_t *state; |
| 274 | |
| 275 | /* Emulate B2 register as the FADT / Linux expects it */ |
| 276 | |
| 277 | reg8 = inb(APM_CNT); |
| 278 | switch (reg8) { |
| 279 | case APM_CNT_CST_CONTROL: |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 280 | /* |
| 281 | * Calling this function seems to cause |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 282 | * some kind of race condition in Linux |
| 283 | * and causes a kernel oops |
| 284 | */ |
| 285 | printk(BIOS_DEBUG, "C-state control\n"); |
| 286 | break; |
| 287 | case APM_CNT_PST_CONTROL: |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 288 | /* |
| 289 | * Calling this function seems to cause |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 290 | * some kind of race condition in Linux |
| 291 | * and causes a kernel oops |
| 292 | */ |
| 293 | printk(BIOS_DEBUG, "P-state control\n"); |
| 294 | break; |
| 295 | case APM_CNT_ACPI_DISABLE: |
| 296 | disable_pm1_control(SCI_EN); |
| 297 | printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); |
| 298 | break; |
| 299 | case APM_CNT_ACPI_ENABLE: |
| 300 | enable_pm1_control(SCI_EN); |
| 301 | printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); |
| 302 | break; |
| 303 | case APM_CNT_GNVS_UPDATE: |
| 304 | if (smm_initialized) { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 305 | printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 306 | return; |
| 307 | } |
| 308 | state = smi_apmc_find_state_save(reg8); |
| 309 | if (state) { |
| 310 | /* EBX in the state save contains the GNVS pointer */ |
| 311 | gnvs = (global_nvs_t *)((uint32_t)state->rbx); |
| 312 | smm_initialized = 1; |
| 313 | printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); |
| 314 | } |
| 315 | break; |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 316 | case APM_CNT_ELOG_GSMI: |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 317 | if (CONFIG(ELOG_GSMI)) |
| 318 | southbridge_smi_gsmi(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 319 | break; |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 320 | case APM_CNT_SMMSTORE: |
| 321 | if (CONFIG(SMMSTORE)) |
| 322 | southbridge_smi_store(); |
| 323 | break; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | mainboard_smi_apmc(reg8); |
| 327 | } |
| 328 | |
| 329 | static void southbridge_smi_pm1(void) |
| 330 | { |
| 331 | uint16_t pm1_sts = clear_pm1_status(); |
| 332 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 333 | /* While OSPM is not active, poweroff immediately on a power button event */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 334 | if (pm1_sts & PWRBTN_STS) { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 335 | /* Power button pressed */ |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 336 | elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 337 | disable_pm1_control(-1UL); |
| 338 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
| 339 | } |
| 340 | } |
| 341 | |
| 342 | static void southbridge_smi_gpe0(void) |
| 343 | { |
| 344 | clear_gpe_status(); |
| 345 | } |
| 346 | |
| 347 | static void southbridge_smi_tco(void) |
| 348 | { |
| 349 | uint32_t tco_sts = clear_tco_status(); |
| 350 | |
| 351 | /* Any TCO event? */ |
| 352 | if (!tco_sts) |
| 353 | return; |
| 354 | |
| 355 | if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ |
| 356 | /* Handle TCO timeout */ |
| 357 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
| 358 | } |
| 359 | } |
| 360 | |
| 361 | static void southbridge_smi_periodic(void) |
| 362 | { |
| 363 | uint32_t reg32; |
| 364 | |
| 365 | reg32 = inl(get_pmbase() + SMI_EN); |
| 366 | |
| 367 | /* Are periodic SMIs enabled? */ |
| 368 | if ((reg32 & PERIODIC_EN) == 0) |
| 369 | return; |
| 370 | |
| 371 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 372 | } |
| 373 | |
| 374 | typedef void (*smi_handler_t)(void); |
| 375 | |
| 376 | static const smi_handler_t southbridge_smi[32] = { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 377 | NULL, /* [0] reserved */ |
| 378 | NULL, /* [1] reserved */ |
| 379 | NULL, /* [2] BIOS_STS */ |
| 380 | NULL, /* [3] LEGACY_USB_STS */ |
| 381 | southbridge_smi_sleep, /* [4] SLP_SMI_STS */ |
| 382 | southbridge_smi_apmc, /* [5] APM_STS */ |
| 383 | NULL, /* [6] SWSMI_TMR_STS */ |
| 384 | NULL, /* [7] reserved */ |
| 385 | southbridge_smi_pm1, /* [8] PM1_STS */ |
| 386 | southbridge_smi_gpe0, /* [9] GPE0_STS */ |
| 387 | NULL, /* [10] reserved */ |
| 388 | NULL, /* [11] reserved */ |
| 389 | NULL, /* [12] reserved */ |
| 390 | southbridge_smi_tco, /* [13] TCO_STS */ |
| 391 | southbridge_smi_periodic, /* [14] PERIODIC_STS */ |
| 392 | NULL, /* [15] SERIRQ_SMI_STS */ |
| 393 | NULL, /* [16] SMBUS_SMI_STS */ |
| 394 | NULL, /* [17] LEGACY_USB2_STS */ |
| 395 | NULL, /* [18] INTEL_USB2_STS */ |
| 396 | NULL, /* [19] reserved */ |
| 397 | NULL, /* [20] PCI_EXP_SMI_STS */ |
| 398 | NULL, /* [21] reserved */ |
| 399 | NULL, /* [22] reserved */ |
| 400 | NULL, /* [23] reserved */ |
| 401 | NULL, /* [24] reserved */ |
| 402 | NULL, /* [25] reserved */ |
| 403 | NULL, /* [26] SPI_STS */ |
| 404 | NULL, /* [27] reserved */ |
| 405 | NULL, /* [28] PUNIT */ |
| 406 | NULL, /* [29] GUNIT */ |
| 407 | NULL, /* [30] reserved */ |
| 408 | NULL /* [31] reserved */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 409 | }; |
| 410 | |
| 411 | void southbridge_smi_handler(void) |
| 412 | { |
| 413 | int i; |
| 414 | uint32_t smi_sts; |
| 415 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 416 | /* |
| 417 | * We need to clear the SMI status registers, or we won't see what's |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 418 | * happening in the following calls. |
| 419 | */ |
| 420 | smi_sts = clear_smi_status(); |
| 421 | |
| 422 | /* Call SMI sub handler for each of the status bits */ |
| 423 | for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { |
| 424 | if (!(smi_sts & (1 << i))) |
| 425 | continue; |
| 426 | |
| 427 | if (southbridge_smi[i] != NULL) { |
| 428 | southbridge_smi[i](); |
| 429 | } else { |
| 430 | printk(BIOS_DEBUG, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 431 | "SMI_STS[%d] occurred, but no handler available.\n", i); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 432 | } |
| 433 | } |
| 434 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 435 | /* |
| 436 | * The GPIO SMI events do not have a status bit in SMI_STS. Therefore, |
| 437 | * these events need to be cleared and checked unconditionally. |
| 438 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 439 | mainboard_smi_gpi(clear_alt_status()); |
| 440 | } |