Angel Pons | 963500f | 2018-04-29 19:56:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 16 | #include <device/pci_ops.h> |
Angel Pons | 963500f | 2018-04-29 19:56:49 +0200 | [diff] [blame] | 17 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 18 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 19 | #include <southbridge/intel/bd82x6x/pch.h> |
| 20 | #include <superio/ite/common/ite.h> |
| 21 | #include <superio/ite/it8728f/it8728f.h> |
| 22 | |
| 23 | #define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO) |
| 24 | #define SERIAL_DEV PNP_DEV(0x2e, 0x01) |
| 25 | |
| 26 | void pch_enable_lpc(void) |
| 27 | { |
Angel Pons | c6b44cd | 2019-03-10 13:21:12 +0100 | [diff] [blame^] | 28 | if (CONFIG(BOARD_GIGABYTE_GA_H61M_S2PV)) { |
| 29 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | |
| 30 | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); |
| 31 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); |
Angel Pons | 963500f | 2018-04-29 19:56:49 +0200 | [diff] [blame] | 32 | |
Angel Pons | c6b44cd | 2019-03-10 13:21:12 +0100 | [diff] [blame^] | 33 | } else if (CONFIG(BOARD_GIGABYTE_GA_H61MA_D3V)) { |
| 34 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | |
| 35 | CNF1_LPC_EN); |
| 36 | } |
Angel Pons | 963500f | 2018-04-29 19:56:49 +0200 | [diff] [blame] | 37 | } |
| 38 | |
| 39 | void mainboard_rcba_config(void) |
| 40 | { |
| 41 | } |
| 42 | |
| 43 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 44 | { 1, 0, 0 }, |
| 45 | { 1, 0, 0 }, |
| 46 | { 1, 0, 1 }, |
| 47 | { 1, 0, 1 }, |
| 48 | { 1, 0, 2 }, |
| 49 | { 1, 0, 2 }, |
| 50 | { 1, 0, 3 }, |
| 51 | { 1, 0, 3 }, |
| 52 | { 1, 0, 4 }, |
| 53 | { 1, 0, 4 }, |
| 54 | { 1, 0, 6 }, |
| 55 | { 1, 0, 5 }, |
| 56 | { 1, 0, 5 }, |
| 57 | { 1, 0, 6 }, |
| 58 | }; |
| 59 | |
| 60 | void mainboard_early_init(int s3resume) |
| 61 | { |
| 62 | } |
| 63 | |
| 64 | void mainboard_config_superio(void) |
| 65 | { |
Angel Pons | c6b44cd | 2019-03-10 13:21:12 +0100 | [diff] [blame^] | 66 | if (!CONFIG(NO_UART_ON_SUPERIO)) { |
| 67 | /* Enable serial port */ |
| 68 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 69 | } |
Angel Pons | 963500f | 2018-04-29 19:56:49 +0200 | [diff] [blame] | 70 | |
Angel Pons | 940bb4e | 2018-06-24 12:02:59 +0200 | [diff] [blame] | 71 | /* Disable SIO WDT which kicks in DualBIOS */ |
| 72 | ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); |
Angel Pons | 963500f | 2018-04-29 19:56:49 +0200 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 76 | { |
| 77 | read_spd(&spd[0], 0x50, id_only); |
| 78 | read_spd(&spd[2], 0x52, id_only); |
| 79 | } |