mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
Tested with SeaBIOS as a payload, booting Arch Linux with
a Linux kernel. The new code is based on autoport and the
existing GA-H61M-S2PV code.
The GA-H61M-S2PV has been boot-tested too, it still boots.
Working:
- S3 suspend/resume
- USB ports and headers (Intel USB2 and EtronTech USB3)
- Gigabit Ethernet
- Integrated DVI/VGA graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1 ports
- PS/2 port with a keyboard
- SATA controllers (Intel SATA2 and Marvell SATA3)
- User-space fan control (fancontrol on Linux)
- Native raminit (4+4GB DDR3-1333)
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
Untested:
- VGA BIOS for integrated graphics init
- Audio: Only front/read outputs has been tested.
- Non-Linux OSes
- ACPI thermal zone and OS-independent fan control
Not working:
- Default IFD defines the BIOS region as the entire flash chip.
Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
index 7154cc9..27fbb2ccc 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
@@ -25,10 +25,15 @@
void pch_enable_lpc(void)
{
- pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
- CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+ if (CONFIG(BOARD_GIGABYTE_GA_H61M_S2PV)) {
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
+ CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+ } else if (CONFIG(BOARD_GIGABYTE_GA_H61MA_D3V)) {
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
+ CNF1_LPC_EN);
+ }
}
void mainboard_rcba_config(void)
@@ -58,8 +63,10 @@
void mainboard_config_superio(void)
{
- /* Enable serial port */
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ if (!CONFIG(NO_UART_ON_SUPERIO)) {
+ /* Enable serial port */
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ }
/* Disable SIO WDT which kicks in DualBIOS */
ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E);