Tim Wawrzynczak | b59980b | 2021-02-04 17:05:30 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_def.h> |
| 7 | #include <intelblocks/gpio.h> |
| 8 | #include <intelblocks/irq.h> |
Tim Wawrzynczak | c657ab9 | 2021-03-01 16:53:22 -0700 | [diff] [blame^] | 9 | #include <intelblocks/lpc_lib.h> |
Tim Wawrzynczak | b59980b | 2021-02-04 17:05:30 -0700 | [diff] [blame] | 10 | #include <southbridge/intel/common/acpi_pirq_gen.h> |
| 11 | #include <stdlib.h> |
| 12 | #include <string.h> |
| 13 | #include <types.h> |
| 14 | |
| 15 | #define MIN_SHARED_IRQ 16 |
| 16 | #define MAX_SHARED_IRQ 23 |
| 17 | #define TOTAL_SHARED_IRQ (MAX_SHARED_IRQ - MIN_SHARED_IRQ + 1) |
| 18 | #define MAX_IRQS 120 |
| 19 | |
| 20 | #define IDX2PIN(i) (enum pci_pin)((i) + PCI_INT_A) |
| 21 | #define PIN2IDX(p) (size_t)((p) - PCI_INT_A) |
| 22 | #define INVALID_IRQ -1 |
| 23 | |
| 24 | struct pin_info { |
| 25 | enum pin_state { |
| 26 | FREE_PIN, |
| 27 | SHARED_IRQ_PIN, |
| 28 | UNIQUE_IRQ_PIN, |
| 29 | } pin_state; |
| 30 | unsigned int usage_count; |
| 31 | unsigned int irq; |
| 32 | }; |
| 33 | |
| 34 | static unsigned int irq_share_count[TOTAL_SHARED_IRQ]; |
| 35 | |
| 36 | /* |
| 37 | * Assign PCI IRQs & pins according to controller rules. |
| 38 | * |
| 39 | * This information is provided to the FSP in order for it to do the |
| 40 | * programming; this is required because the FSP is also responsible for |
| 41 | * enabling some PCI devices so they will show up on their respective PCI |
| 42 | * buses. The FSP & PCH BIOS Specification contain rules for how certain IPs |
| 43 | * require their interrupt pin and interrupt line to be programmed. |
| 44 | * |
| 45 | * IOAPIC IRQs are used for PCI devices & GPIOs. The GPIO IRQs are fixed in |
| 46 | * hardware (the IRQ field is RO), and often start at 24, which means |
| 47 | * conflicts with PCI devices (if using the default FSP configuration) are very |
| 48 | * possible. |
| 49 | * |
| 50 | * These are the rules: |
| 51 | * 1) One entry per slot/function |
| 52 | * 2) Functions using PIRQs must use IOxAPIC IRQs 16-23 |
| 53 | * 3) Single-function devices must use INTA |
| 54 | * 4) Each slot must have consistent INTx<->PIRQy mappings |
| 55 | * 5) Some functions have special interrupt pin requirements (FIXED_INT_ANY_PIRQ) |
| 56 | * 6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIRQ) |
| 57 | * 7) Some functions require a unique IRQ number (mostly LPSS devices, DIRECT_IRQ) |
| 58 | * 8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes its |
| 59 | * IRQ through IO-APIC. |
| 60 | */ |
| 61 | |
| 62 | static int find_free_unique_irq(void) |
| 63 | { |
| 64 | static unsigned int next_irq = MAX_SHARED_IRQ + 1; |
| 65 | |
| 66 | while (next_irq < MAX_IRQS && gpio_routes_ioapic_irq(next_irq)) |
| 67 | ++next_irq; |
| 68 | |
| 69 | if (next_irq == MAX_IRQS) |
| 70 | return INVALID_IRQ; |
| 71 | |
| 72 | return next_irq++; |
| 73 | } |
| 74 | |
| 75 | static enum pci_pin find_free_pin(const struct pin_info pin_info[PCI_INT_MAX]) |
| 76 | { |
| 77 | for (size_t pin_idx = 0; pin_idx < PCI_INT_MAX; pin_idx++) { |
| 78 | if (pin_info[pin_idx].pin_state == FREE_PIN) |
| 79 | return IDX2PIN(pin_idx); |
| 80 | } |
| 81 | |
| 82 | return PCI_INT_NONE; |
| 83 | } |
| 84 | |
| 85 | static enum pci_pin find_shareable_pin(const struct pin_info pin_info[PCI_INT_MAX]) |
| 86 | { |
| 87 | unsigned int least_shared = 255; |
| 88 | int least_index = -1; |
| 89 | |
| 90 | for (size_t pin_idx = 0; pin_idx < PCI_INT_MAX; pin_idx++) { |
| 91 | if (pin_info[pin_idx].pin_state == SHARED_IRQ_PIN && |
| 92 | pin_info[pin_idx].usage_count < least_shared) { |
| 93 | least_shared = pin_info[pin_idx].usage_count; |
| 94 | least_index = pin_idx; |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | if (least_index < 0) |
| 99 | return PCI_INT_NONE; |
| 100 | |
| 101 | return IDX2PIN(least_index); |
| 102 | } |
| 103 | |
| 104 | static enum pirq find_global_least_used_pirq(void) |
| 105 | { |
| 106 | unsigned int least_shared = 255; |
| 107 | int least_index = -1; |
| 108 | |
| 109 | for (size_t i = 0; i < TOTAL_SHARED_IRQ; i++) { |
| 110 | if (irq_share_count[i] < least_shared) { |
| 111 | least_shared = irq_share_count[i]; |
| 112 | least_index = i; |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | if (least_index >= 0) |
| 117 | return (enum pirq)least_index + PIRQ_A; |
| 118 | |
| 119 | return PIRQ_INVALID; |
| 120 | } |
| 121 | |
| 122 | |
| 123 | static int pirq_to_irq(enum pirq pirq) |
| 124 | { |
| 125 | return pirq_idx(pirq) + MIN_SHARED_IRQ; |
| 126 | } |
| 127 | |
| 128 | static bool assign_pirq(struct pin_info pin_info[PCI_INT_MAX], enum pci_pin pin, enum pirq pirq) |
| 129 | { |
| 130 | if (pirq < PIRQ_A || pirq > PIRQ_H) { |
| 131 | printk(BIOS_ERR, "ERROR: Invalid pirq constraint %u\n", pirq); |
| 132 | return false; |
| 133 | } |
| 134 | |
| 135 | const int irq = pirq_to_irq(pirq); |
| 136 | pin_info[PIN2IDX(pin)].irq = irq; |
| 137 | irq_share_count[pirq_idx(pirq)]++; |
| 138 | return true; |
| 139 | } |
| 140 | |
| 141 | static bool assign_pin(enum pci_pin pin, unsigned int fn, enum pin_state state, |
| 142 | struct pin_info *pin_info, |
| 143 | enum pci_pin fn_pin_map[MAX_FNS]) |
| 144 | { |
| 145 | if (pin < PCI_INT_A || pin > PCI_INT_D) { |
| 146 | printk(BIOS_ERR, "ERROR: Invalid pin constraint %u\n", pin); |
| 147 | return false; |
| 148 | } |
| 149 | |
| 150 | const size_t pin_idx = PIN2IDX(pin); |
| 151 | pin_info[pin_idx].pin_state = state; |
| 152 | pin_info[pin_idx].usage_count++; |
| 153 | fn_pin_map[fn] = pin; |
| 154 | |
| 155 | return true; |
| 156 | } |
| 157 | |
| 158 | static bool assign_fixed_pins(const struct slot_irq_constraints *constraints, |
| 159 | struct pin_info *pin_info, enum pci_pin fn_pin_map[MAX_FNS]) |
| 160 | { |
| 161 | for (size_t i = 0; i < MAX_FNS; i++) { |
| 162 | const enum pci_pin fixed_int_pin = constraints->fns[i].fixed_int_pin; |
| 163 | if (fixed_int_pin == PCI_INT_NONE) |
| 164 | continue; |
| 165 | |
| 166 | if (!assign_pin(fixed_int_pin, i, SHARED_IRQ_PIN, pin_info, fn_pin_map)) |
| 167 | return false; |
| 168 | } |
| 169 | |
| 170 | return true; |
| 171 | } |
| 172 | |
| 173 | static bool assign_fixed_pirqs(const struct slot_irq_constraints *constraints, |
| 174 | struct pin_info *pin_info, enum pci_pin fn_pin_map[MAX_FNS]) |
| 175 | { |
| 176 | for (size_t i = 0; i < MAX_FNS; i++) { |
| 177 | const enum pirq fixed_pirq = constraints->fns[i].fixed_pirq; |
| 178 | if (fixed_pirq == PIRQ_INVALID) |
| 179 | continue; |
| 180 | |
| 181 | /* A constraint with a fixed pirq is assumed to also have a |
| 182 | fixed pin */ |
| 183 | const enum pci_pin pin = fn_pin_map[i]; |
| 184 | if (pin == PCI_INT_NONE) { |
| 185 | printk(BIOS_ERR, "ERROR: Slot %u, pirq %u, no pin for function %lu\n", |
| 186 | constraints->slot, fixed_pirq, i); |
| 187 | return false; |
| 188 | } |
| 189 | |
| 190 | if (!assign_pirq(pin_info, pin, fixed_pirq)) |
| 191 | return false; |
| 192 | } |
| 193 | |
| 194 | return true; |
| 195 | } |
| 196 | |
| 197 | static bool assign_direct_irqs(const struct slot_irq_constraints *constraints, |
| 198 | struct pin_info *pin_info, enum pci_pin fn_pin_map[MAX_FNS]) |
| 199 | { |
| 200 | for (size_t i = 0; i < MAX_FNS; i++) { |
| 201 | if (constraints->fns[i].irq_route != IRQ_DIRECT) |
| 202 | continue; |
| 203 | |
| 204 | enum pci_pin pin = find_free_pin(pin_info); |
| 205 | if (pin == PCI_INT_NONE) |
| 206 | return false; |
| 207 | |
| 208 | if (!assign_pin(pin, i, UNIQUE_IRQ_PIN, pin_info, fn_pin_map)) |
| 209 | return false; |
| 210 | |
| 211 | const int irq = find_free_unique_irq(); |
| 212 | if (irq == INVALID_IRQ) { |
| 213 | printk(BIOS_ERR, "ERROR: No free unique IRQs found\n"); |
| 214 | return false; |
| 215 | } |
| 216 | |
| 217 | const size_t pin_idx = PIN2IDX(pin); |
| 218 | pin_info[pin_idx].irq = irq; |
| 219 | } |
| 220 | |
| 221 | return true; |
| 222 | } |
| 223 | |
| 224 | static bool assign_shareable_pins(const struct slot_irq_constraints *constraints, |
| 225 | struct pin_info *pin_info, enum pci_pin fn_pin_map[MAX_FNS]) |
| 226 | { |
| 227 | for (size_t i = 0; i < MAX_FNS; i++) { |
| 228 | if (constraints->fns[i].irq_route != IRQ_PIRQ) |
| 229 | continue; |
| 230 | |
| 231 | if (fn_pin_map[i] == PCI_INT_NONE) { |
| 232 | enum pci_pin pin = find_free_pin(pin_info); |
| 233 | if (pin == PCI_INT_NONE) { |
| 234 | pin = find_shareable_pin(pin_info); |
| 235 | |
| 236 | if (pin == PCI_INT_NONE) { |
| 237 | printk(BIOS_ERR, "ERROR: No shareable pins found\n"); |
| 238 | return false; |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | if (!assign_pin(pin, i, SHARED_IRQ_PIN, pin_info, fn_pin_map)) |
| 243 | return false; |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | return true; |
| 248 | } |
| 249 | |
| 250 | static bool assign_pirqs(struct pin_info pin_info[PCI_INT_MAX]) |
| 251 | { |
| 252 | for (size_t pin_idx = 0; pin_idx < PCI_INT_MAX; pin_idx++) { |
| 253 | if (pin_info[pin_idx].pin_state != SHARED_IRQ_PIN || pin_info[pin_idx].irq != 0) |
| 254 | continue; |
| 255 | |
| 256 | enum pirq pirq = find_global_least_used_pirq(); |
| 257 | if (pirq == PIRQ_INVALID) |
| 258 | return false; |
| 259 | |
| 260 | if (!assign_pirq(pin_info, IDX2PIN(pin_idx), pirq)) |
| 261 | return false; |
| 262 | } |
| 263 | |
| 264 | return true; |
| 265 | } |
| 266 | |
| 267 | static void add_entry(struct pci_irq_entry **head, pci_devfn_t devfn, enum pci_pin pin, |
| 268 | unsigned int irq) |
| 269 | { |
| 270 | struct pci_irq_entry *entry = malloc(sizeof(*entry)); |
| 271 | struct pci_irq_entry **tmp = head; |
| 272 | |
| 273 | entry->devfn = devfn; |
| 274 | entry->pin = pin; |
| 275 | entry->irq = irq; |
| 276 | entry->next = NULL; |
| 277 | |
| 278 | while (*tmp) |
| 279 | tmp = &(*tmp)->next; |
| 280 | |
| 281 | *tmp = entry; |
| 282 | } |
| 283 | |
| 284 | static void add_slot_entries(struct pci_irq_entry **head, unsigned int slot, |
| 285 | struct pin_info pin_info[PCI_INT_MAX], |
| 286 | const enum pci_pin fn_pin_map[MAX_FNS]) |
| 287 | { |
| 288 | for (size_t fn = 0; fn < MAX_FNS; fn++) { |
| 289 | if (fn_pin_map[fn] == PCI_INT_NONE) |
| 290 | continue; |
| 291 | |
| 292 | const size_t pin_idx = PIN2IDX(fn_pin_map[fn]); |
| 293 | add_entry(head, PCI_DEVFN(slot, fn), fn_pin_map[fn], pin_info[pin_idx].irq); |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | static bool assign_slot(struct pci_irq_entry **head, |
| 298 | const struct slot_irq_constraints *constraints) |
| 299 | { |
| 300 | struct pin_info pin_info[PCI_INT_MAX] = {0}; |
| 301 | enum pci_pin fn_pin_map[MAX_FNS] = {0}; |
| 302 | |
| 303 | /* The order in which pins are assigned is important in that strict constraints must |
| 304 | * be resolved first. This means fixed_int_pin -> fixed_pirq -> direct route -> |
| 305 | * shared pins -> shared pirqs |
| 306 | */ |
| 307 | if (!assign_fixed_pins(constraints, pin_info, fn_pin_map)) |
| 308 | return false; |
| 309 | |
| 310 | if (!assign_fixed_pirqs(constraints, pin_info, fn_pin_map)) |
| 311 | return false; |
| 312 | |
| 313 | if (!assign_direct_irqs(constraints, pin_info, fn_pin_map)) |
| 314 | return false; |
| 315 | |
| 316 | if (!assign_shareable_pins(constraints, pin_info, fn_pin_map)) |
| 317 | return false; |
| 318 | |
| 319 | if (!assign_pirqs(pin_info)) |
| 320 | return false; |
| 321 | |
| 322 | add_slot_entries(head, constraints->slot, pin_info, fn_pin_map); |
| 323 | return true; |
| 324 | } |
| 325 | |
| 326 | const struct pci_irq_entry *assign_pci_irqs(const struct slot_irq_constraints *constraints, |
| 327 | size_t num_slots) |
| 328 | { |
| 329 | struct pci_irq_entry *entries = NULL; |
| 330 | |
| 331 | for (size_t i = 0; i < num_slots; i++) { |
| 332 | if (!assign_slot(&entries, &constraints[i])) |
| 333 | return NULL; |
| 334 | } |
| 335 | |
| 336 | const struct pci_irq_entry *entry = entries; |
| 337 | while (entry) { |
| 338 | printk(BIOS_INFO, "PCI %2X.%X, %s, using IRQ #%d\n", |
| 339 | PCI_SLOT(entry->devfn), PCI_FUNC(entry->devfn), |
| 340 | pin_to_str(entry->pin), entry->irq); |
| 341 | |
| 342 | entry = entry->next; |
| 343 | } |
| 344 | |
| 345 | return entries; |
| 346 | } |
Tim Wawrzynczak | c657ab9 | 2021-03-01 16:53:22 -0700 | [diff] [blame^] | 347 | |
| 348 | static enum pirq irq_to_pirq(unsigned int irq) |
| 349 | { |
| 350 | if (irq >= MIN_SHARED_IRQ && irq <= MAX_SHARED_IRQ) |
| 351 | return (enum pirq)(irq - MIN_SHARED_IRQ + PIRQ_A); |
| 352 | else |
| 353 | /* |
| 354 | * Unknown if devices that require unique IRQs will |
| 355 | * even work in legacy PIC mode, given they cannot map |
| 356 | * to a PIRQ, therefore skip adding an entry. |
| 357 | */ |
| 358 | return PIRQ_INVALID; |
| 359 | } |
| 360 | |
| 361 | void generate_pin_irq_map(const struct pci_irq_entry *entries) |
| 362 | { |
| 363 | struct slot_pin_irq_map *pin_irq_map; |
| 364 | const uint8_t *legacy_pirq_routing; |
| 365 | struct pic_pirq_map pirq_map = {0}; |
| 366 | size_t map_count = 0; |
| 367 | size_t pirq_routes; |
| 368 | size_t i; |
| 369 | |
| 370 | pin_irq_map = calloc(MAX_SLOTS, sizeof(struct slot_pin_irq_map) * PCI_INT_MAX); |
| 371 | |
| 372 | pirq_map.type = PIRQ_GSI; |
| 373 | legacy_pirq_routing = lpc_get_pic_pirq_routing(&pirq_routes); |
| 374 | for (i = 0; i < PIRQ_COUNT && i < pirq_routes; i++) |
| 375 | pirq_map.gsi[i] = legacy_pirq_routing[i]; |
| 376 | |
| 377 | const struct pci_irq_entry *entry = entries; |
| 378 | while (entry) { |
| 379 | const unsigned int slot = PCI_SLOT(entry->devfn); |
| 380 | |
| 381 | if (is_slot_pin_assigned(pin_irq_map, map_count, slot, entry->pin)) { |
| 382 | entry = entry->next; |
| 383 | continue; |
| 384 | } |
| 385 | |
| 386 | pin_irq_map[map_count].slot = slot; |
| 387 | pin_irq_map[map_count].pin = entry->pin; |
| 388 | pin_irq_map[map_count].apic_gsi = entry->irq; |
| 389 | pin_irq_map[map_count].pic_pirq = irq_to_pirq(entry->irq); |
| 390 | map_count++; |
| 391 | entry = entry->next; |
| 392 | } |
| 393 | |
| 394 | intel_write_pci0_PRT(pin_irq_map, map_count, &pirq_map); |
| 395 | free(pin_irq_map); |
| 396 | } |