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review.coreboot.org / coreboot / b59980b54ebe22cc4dcbc0da63206c7f9ec47c28
commitb59980b54ebe22cc4dcbc0da63206c7f9ec47c28[log] [tgz]
authorTim Wawrzynczak <twawrzynczak@chromium.org>Thu Feb 04 17:05:30 2021 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>Tue Jun 29 21:50:45 2021 +0000
treef906bbbd963948d251692d0c0663d60acba7a616
parentef16df27826522b158809a31bef71e079e67a61c [diff]
soc/intel/common: Add new IRQ module

The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if
the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of
rules that the input IRQ table must conform to:
1) One entry per slot/function
2) Functions using PIRQs must use IOxAPIC IRQs 16-23
3) Single-function devices must use INTA
4) Each slot must have consistent INTx<->PIRQy mappings
5) Some functions have special interrupt pin requirements
6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN)
7) Some functions require a unique IRQ number
8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes
   its IRQ through IO-APIC.

Since the FSP has no visibility into the actual GPIOs used on the board
when GpioOverride is selected, IRQ conflicts can occur between PCI
devices and GPIOs. This patch gives SoC code the ability to generate a
table of PCI IRQs that will meet the BWG/FSP rules and also not conflict
with GPIO IRQs.

BUG=b:130217151, b:171580862, b:176858827
TEST=Boot with patch series on volteer, verify IO-APIC IRQs in
`/proc/interrupts` match what is expected. No `GSI INT` or
`could not derive routing` messages seen in `dmesg` output.
Verified TPM, touchpad, touchscreen IRQs all function as expected.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49408
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
4 files changed
tree: f906bbbd963948d251692d0c0663d60acba7a616
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.