| Martin Roth | 39065ef | 2024-02-16 11:00:32 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 3 | config BOARD_PRODRIVE_ATLAS_BASEBOARD |
| 4 | def_bool n |
| 5 | select BOARD_ROMSIZE_KB_32768 |
| Lean Sheng Tan | a91821b | 2022-07-19 17:01:36 +0200 | [diff] [blame] | 6 | select INTEL_LPSS_UART_FOR_CONSOLE |
| Lean Sheng Tan | bb92a7f | 2022-04-07 15:23:13 +0200 | [diff] [blame] | 7 | select EC_ACPI |
| Lean Sheng Tan | dfe2ef0 | 2022-09-06 19:46:48 +0200 | [diff] [blame] | 8 | select FSP_TYPE_IOT |
| Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 9 | select HAVE_ACPI_TABLES |
| Lean Sheng Tan | cb14e86 | 2022-06-03 08:56:47 +0200 | [diff] [blame] | 10 | select INTEL_GMA_HAVE_VBT |
| Lean Sheng Tan | 9aa7a25 | 2022-04-19 17:34:46 +0200 | [diff] [blame] | 11 | select MAINBOARD_HAS_TPM2 |
| Lean Sheng Tan | cb14e86 | 2022-06-03 08:56:47 +0200 | [diff] [blame] | 12 | select MAINBOARD_USES_IFD_EC_REGION |
| Eric Lai | 08b477e | 2022-04-22 11:11:47 +0800 | [diff] [blame] | 13 | select MEMORY_MAPPED_TPM |
| Lean Sheng Tan | dfe2ef0 | 2022-09-06 19:46:48 +0200 | [diff] [blame] | 14 | select PCIEXP_SUPPORT_RESIZABLE_BARS |
| Lean Sheng Tan | cb14e86 | 2022-06-03 08:56:47 +0200 | [diff] [blame] | 15 | select SOC_INTEL_ALDERLAKE_PCH_P |
| Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 16 | |
| Felix Singer | d684d27 | 2023-05-08 19:57:44 +0200 | [diff] [blame] | 17 | config BOARD_PRODRIVE_ATLAS |
| 18 | select BOARD_PRODRIVE_ATLAS_BASEBOARD |
| 19 | |
| Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 20 | if BOARD_PRODRIVE_ATLAS_BASEBOARD |
| 21 | |
| Lean Sheng Tan | 2ddcf40 | 2022-09-07 16:25:52 +0200 | [diff] [blame] | 22 | config ATLAS_ENABLE_SAGV |
| 23 | bool "Enable SaGv" |
| Lean Sheng Tan | 50c56fb | 2023-01-23 14:47:22 +0100 | [diff] [blame] | 24 | default n |
| Lean Sheng Tan | 2ddcf40 | 2022-09-07 16:25:52 +0200 | [diff] [blame] | 25 | |
| Maximilian Brune | 0925bda | 2022-10-25 15:03:40 +0200 | [diff] [blame] | 26 | config ATLAS_ENABLE_IBECC |
| 27 | bool "Enable IBECC" |
| 28 | help |
| 29 | Enables In Band Error Correction Code. It's only needed for endurance testing |
| 30 | and therefore not always required. |
| 31 | default n |
| 32 | |
| Sean Rhodes | 1d41f90 | 2023-04-13 12:08:58 +0100 | [diff] [blame] | 33 | config D3COLD_SUPPORT |
| 34 | default n |
| 35 | |
| Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 36 | config MAINBOARD_FAMILY |
| 37 | string |
| 38 | default "PRODRIVE_ATLAS_SERIES" |
| 39 | |
| 40 | config MAINBOARD_PART_NUMBER |
| 41 | default "Atlas ADL-P" |
| 42 | |
| 43 | config MAINBOARD_DIR |
| 44 | default "prodrive/atlas" |
| 45 | |
| 46 | config MAINBOARD_SMBIOS_MANUFACTURER |
| 47 | string |
| 48 | default "Prodrive Technologies B.V." |
| 49 | |
| Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 50 | config UART_FOR_CONSOLE |
| 51 | int |
| 52 | default 0 |
| 53 | |
| Lean Sheng Tan | 0cc82d6 | 2022-06-03 09:39:48 +0200 | [diff] [blame] | 54 | config CBFS_SIZE |
| 55 | default 0x800000 |
| 56 | |
| Maximilian Brune | 4f13239 | 2023-02-23 19:07:41 +0100 | [diff] [blame] | 57 | config PCIEXP_ASPM |
| 58 | bool |
| 59 | default n |
| 60 | help |
| 61 | FSP is already taking care of ASPM, which is configured through the devicetree in coreboot |
| 62 | on Alderlake Platforms. Disable it to save some boot time. |
| 63 | |
| 64 | config PCIEXP_L1_SUB_STATE |
| 65 | bool |
| 66 | default n |
| 67 | help |
| 68 | Enabling PCIe L1 sub states is already done in FSP. |
| 69 | Disable it to save some boot time. |
| 70 | |
| 71 | config PCIEXP_CLK_PM |
| 72 | bool |
| 73 | default n |
| 74 | help |
| 75 | Enabling PCIe clock power management is already done in FSP. |
| 76 | Disable it to save some boot time |
| 77 | |
| Lean Sheng Tan | 003fe29 | 2022-09-07 21:07:29 +0200 | [diff] [blame] | 78 | # This platform has limited means to display POST codes |
| 79 | config NO_POST |
| 80 | default y |
| 81 | |
| Lean Sheng Tan | e98dd0a | 2022-09-12 15:26:43 +0200 | [diff] [blame] | 82 | config ENABLE_BUZZER_SUPPORT |
| 83 | bool "Enable Buzzer support" |
| 84 | default y |
| 85 | select USE_LEGACY_8254_TIMER |
| 86 | help |
| 87 | 8254 timer is required for buzzer support on GPP_B14 (based on Intel doc 621483, |
| 88 | 26.1.1 - NMI_STS_CNT). However since 8254 timer clock gating has to be enabled for |
| 89 | S0ix support, enabling buzzer will disable s0ix. |
| 90 | |
| Lean Sheng Tan | dfe2ef0 | 2022-09-06 19:46:48 +0200 | [diff] [blame] | 91 | config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS |
| 92 | int |
| 93 | default 32 |
| 94 | |
| Lean Sheng Tan | 5352d22 | 2022-01-07 13:48:13 +0100 | [diff] [blame] | 95 | endif #BOARD_PRODRIVE_ATLAS_BASEBOARD |