Gitiles
Code Review Sign In
review.coreboot.org / coreboot / d684d277a42d354eb030768b726ff0cae6f68056 / . / src / mainboard / prodrive / atlas / Kconfig
blob: e4be9463fdba4fa7baec05e23807539acdcde660 [file] [log] [blame]
Lean Sheng Tan5352d222022-01-07 13:48:13 +0100[diff] [blame]1config BOARD_PRODRIVE_ATLAS_BASEBOARD
2 def_bool n
3 select BOARD_ROMSIZE_KB_32768
Lean Sheng Tana91821b2022-07-19 17:01:36 +0200[diff] [blame]4 select INTEL_LPSS_UART_FOR_CONSOLE
Lean Sheng Tanbb92a7f2022-04-07 15:23:13 +0200[diff] [blame]5 select EC_ACPI
Lean Sheng Tandfe2ef02022-09-06 19:46:48 +0200[diff] [blame]6 select FSP_TYPE_IOT
Lean Sheng Tan5352d222022-01-07 13:48:13 +0100[diff] [blame]7 select HAVE_ACPI_TABLES
Lean Sheng Tancb14e862022-06-03 08:56:47 +0200[diff] [blame]8 select INTEL_GMA_HAVE_VBT
Lean Sheng Tan9aa7a252022-04-19 17:34:46 +0200[diff] [blame]9 select MAINBOARD_HAS_TPM2
Lean Sheng Tancb14e862022-06-03 08:56:47 +0200[diff] [blame]10 select MAINBOARD_USES_IFD_EC_REGION
Eric Lai08b477e2022-04-22 11:11:47 +0800[diff] [blame]11 select MEMORY_MAPPED_TPM
Lean Sheng Tandfe2ef02022-09-06 19:46:48 +0200[diff] [blame]12 select PCIEXP_SUPPORT_RESIZABLE_BARS
Lean Sheng Tancb14e862022-06-03 08:56:47 +0200[diff] [blame]13 select SOC_INTEL_ALDERLAKE_PCH_P
Lean Sheng Tan5352d222022-01-07 13:48:13 +0100[diff] [blame]14
Felix Singerd684d272023-05-08 19:57:44 +0200[diff] [blame^]15config BOARD_PRODRIVE_ATLAS
16 select BOARD_PRODRIVE_ATLAS_BASEBOARD
17
Lean Sheng Tan5352d222022-01-07 13:48:13 +0100[diff] [blame]18if BOARD_PRODRIVE_ATLAS_BASEBOARD
19
Lean Sheng Tan2ddcf402022-09-07 16:25:52 +0200[diff] [blame]20config ATLAS_ENABLE_SAGV
21 bool "Enable SaGv"
Lean Sheng Tan50c56fb2023-01-23 14:47:22 +0100[diff] [blame]22 default n
Lean Sheng Tan2ddcf402022-09-07 16:25:52 +0200[diff] [blame]23
Maximilian Brune0925bda2022-10-25 15:03:40 +0200[diff] [blame]24config ATLAS_ENABLE_IBECC
25 bool "Enable IBECC"
26 help
27 Enables In Band Error Correction Code. It's only needed for endurance testing
28 and therefore not always required.
29 default n
30
Sean Rhodes1d41f902023-04-13 12:08:58 +0100[diff] [blame]31config D3COLD_SUPPORT
32 default n
33
Lean Sheng Tan5352d222022-01-07 13:48:13 +0100[diff] [blame]34config MAINBOARD_FAMILY
35 string
36 default "PRODRIVE_ATLAS_SERIES"
37
38config MAINBOARD_PART_NUMBER
39 default "Atlas ADL-P"
40
41config MAINBOARD_DIR
42 default "prodrive/atlas"
43
44config MAINBOARD_SMBIOS_MANUFACTURER
45 string
46 default "Prodrive Technologies B.V."
47
48config DIMM_SPD_SIZE
49 default 512
50
51config UART_FOR_CONSOLE
52 int
53 default 0
54
Lean Sheng Tan0cc82d62022-06-03 09:39:48 +0200[diff] [blame]55config CBFS_SIZE
56 default 0x800000
57
Maximilian Brune4f132392023-02-23 19:07:41 +0100[diff] [blame]58config PCIEXP_ASPM
59 bool
60 default n
61 help
62 FSP is already taking care of ASPM, which is configured through the devicetree in coreboot
63 on Alderlake Platforms. Disable it to save some boot time.
64
65config PCIEXP_L1_SUB_STATE
66 bool
67 default n
68 help
69 Enabling PCIe L1 sub states is already done in FSP.
70 Disable it to save some boot time.
71
72config PCIEXP_CLK_PM
73 bool
74 default n
75 help
76 Enabling PCIe clock power management is already done in FSP.
77 Disable it to save some boot time
78
Lean Sheng Tan003fe292022-09-07 21:07:29 +0200[diff] [blame]79# This platform has limited means to display POST codes
80config NO_POST
81 default y
82
Lean Sheng Tane98dd0a2022-09-12 15:26:43 +0200[diff] [blame]83config ENABLE_BUZZER_SUPPORT
84 bool "Enable Buzzer support"
85 default y
86 select USE_LEGACY_8254_TIMER
87 help
88 8254 timer is required for buzzer support on GPP_B14 (based on Intel doc 621483,
89 26.1.1 - NMI_STS_CNT). However since 8254 timer clock gating has to be enabled for
90 S0ix support, enabling buzzer will disable s0ix.
91
Lean Sheng Tandfe2ef02022-09-06 19:46:48 +0200[diff] [blame]92config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
93 int
94 default 32
95
Lean Sheng Tan5352d222022-01-07 13:48:13 +0100[diff] [blame]96endif #BOARD_PRODRIVE_ATLAS_BASEBOARD