Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Iru Cai | 3364203 | 2019-06-11 14:24:43 +0800 | [diff] [blame] | 4 | #include <console/usb.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <string.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <cbmem.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | #include <cbfs.h> |
Elyes HAOUAS | 82d4642 | 2019-04-28 18:01:48 +0200 | [diff] [blame] | 8 | #include <cf9_reset.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include <ip_checksum.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 10 | #include <memory_info.h> |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 11 | #include <mrc_cache.h> |
Angel Pons | d99b693 | 2021-03-12 17:37:42 +0100 | [diff] [blame^] | 12 | #include <device/device.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | #include <device/pci_def.h> |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 14 | #include <device/pci_ops.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 15 | #include <device/dram/ddr3.h> |
Angel Pons | d99b693 | 2021-03-12 17:37:42 +0100 | [diff] [blame^] | 16 | #include <northbridge/intel/haswell/chip.h> |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 17 | #include <smbios.h> |
| 18 | #include <spd.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 19 | #include <security/vboot/vboot_common.h> |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 20 | #include <commonlib/region.h> |
Angel Pons | d99b693 | 2021-03-12 17:37:42 +0100 | [diff] [blame^] | 21 | #include <southbridge/intel/lynxpoint/me.h> |
| 22 | #include <southbridge/intel/lynxpoint/pch.h> |
| 23 | #include <timestamp.h> |
Elyes HAOUAS | 030d338 | 2021-02-12 08:17:35 +0100 | [diff] [blame] | 24 | #include <types.h> |
| 25 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 26 | #include "raminit.h" |
| 27 | #include "pei_data.h" |
| 28 | #include "haswell.h" |
| 29 | |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 30 | #define MRC_CACHE_VERSION 1 |
| 31 | |
Angel Pons | d99b693 | 2021-03-12 17:37:42 +0100 | [diff] [blame^] | 32 | static void save_mrc_data(struct pei_data *pei_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 33 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | /* Save the MRC S3 restore data to cbmem */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 35 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, |
| 36 | pei_data->mrc_output_len); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | } |
| 38 | |
| 39 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 40 | { |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 41 | size_t mrc_size; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 42 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 43 | /* Preset just in case there is an error */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | pei_data->mrc_input = NULL; |
| 45 | pei_data->mrc_input_len = 0; |
| 46 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 47 | pei_data->mrc_input = |
| 48 | mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 49 | MRC_CACHE_VERSION, |
| 50 | &mrc_size); |
| 51 | if (!pei_data->mrc_input) |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 52 | /* Error message printed in find_current_mrc_cache */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 54 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 55 | pei_data->mrc_input_len = mrc_size; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 56 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 57 | printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__, |
| 58 | pei_data->mrc_input, mrc_size); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 59 | } |
| 60 | |
Angel Pons | 0117e4e | 2020-10-13 23:34:27 +0200 | [diff] [blame] | 61 | static const char *const ecc_decoder[] = { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | "inactive", |
| 63 | "active on IO", |
| 64 | "disabled on IO", |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 65 | "active", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | }; |
| 67 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 68 | /* Print out the memory controller configuration, as per the values in its registers. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 69 | static void report_memory_config(void) |
| 70 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | int i; |
| 72 | |
Angel Pons | 82654b3 | 2020-10-13 21:45:45 +0200 | [diff] [blame] | 73 | const u32 addr_decoder_common = MCHBAR32(MAD_CHNL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 74 | |
| 75 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 76 | (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); |
| 77 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 78 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 79 | (addr_decoder_common >> 0) & 3, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 80 | (addr_decoder_common >> 2) & 3, |
| 81 | (addr_decoder_common >> 4) & 3); |
| 82 | |
Angel Pons | 82654b3 | 2020-10-13 21:45:45 +0200 | [diff] [blame] | 83 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 84 | const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 85 | |
| 86 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); |
| 87 | printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 88 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 89 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 90 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 91 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 92 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 93 | |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 94 | printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 95 | ((ch_conf >> 0) & 0xff) * 256, |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 96 | ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 97 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 98 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 99 | |
Duncan Laurie | 8d77402 | 2013-10-22 16:32:49 -0700 | [diff] [blame] | 100 | printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 101 | ((ch_conf >> 8) & 0xff) * 256, |
Ryan Salsamendi | dab81a4 | 2017-06-30 17:36:41 -0700 | [diff] [blame] | 102 | ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 103 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 104 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | /** |
| 109 | * Find PEI executable in coreboot filesystem and execute it. |
| 110 | * |
| 111 | * @param pei_data: configuration data for UEFI PEI reference code |
| 112 | */ |
Angel Pons | d99b693 | 2021-03-12 17:37:42 +0100 | [diff] [blame^] | 113 | static void sdram_initialize(struct pei_data *pei_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 114 | { |
Angel Pons | 1ca6b53 | 2020-10-13 23:43:00 +0200 | [diff] [blame] | 115 | int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); |
| 116 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 117 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 118 | |
Shelley Chen | 6615c6e | 2020-10-27 15:58:31 -0700 | [diff] [blame] | 119 | /* |
| 120 | * Always pass in mrc_cache data. The driver will determine |
| 121 | * whether to use the data or not. |
| 122 | */ |
| 123 | prepare_mrc_cache(pei_data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 125 | /* If MRC data is not found, we cannot continue S3 resume */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
Duncan Laurie | 727b545 | 2013-08-08 16:28:41 -0700 | [diff] [blame] | 127 | post_code(POST_RESUME_FAILURE); |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 128 | printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); |
Elyes HAOUAS | 82d4642 | 2019-04-28 18:01:48 +0200 | [diff] [blame] | 129 | system_reset(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | /* Pass console handler in pei_data */ |
Kyösti Mälkki | 657e0be | 2014-02-04 19:03:57 +0200 | [diff] [blame] | 133 | pei_data->tx_byte = do_putchar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 134 | |
Arthur Heymans | 8da2fa0 | 2018-06-06 10:35:45 +0200 | [diff] [blame] | 135 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 136 | * Locate and call UEFI System Agent binary. The binary needs to be at a fixed offset |
Julius Werner | 9d0cc2a | 2020-01-22 18:00:18 -0800 | [diff] [blame] | 137 | * in the flash and can therefore only reside in the COREBOOT fmap region. We don't care |
| 138 | * about leaking the mapping. |
Arthur Heymans | 8da2fa0 | 2018-06-06 10:35:45 +0200 | [diff] [blame] | 139 | */ |
Julius Werner | 9d0cc2a | 2020-01-22 18:00:18 -0800 | [diff] [blame] | 140 | entry = cbfs_ro_map("mrc.bin", NULL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | if (entry) { |
Angel Pons | 1ca6b53 | 2020-10-13 23:43:00 +0200 | [diff] [blame] | 142 | int rv = entry(pei_data); |
Iru Cai | 3364203 | 2019-06-11 14:24:43 +0800 | [diff] [blame] | 143 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 144 | /* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */ |
Iru Cai | 3364203 | 2019-06-11 14:24:43 +0800 | [diff] [blame] | 145 | if (CONFIG(USBDEBUG_IN_PRE_RAM)) |
| 146 | usbdebug_hw_init(true); |
| 147 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | if (rv) { |
| 149 | switch (rv) { |
| 150 | case -1: |
| 151 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 152 | break; |
| 153 | case -2: |
| 154 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 155 | break; |
| 156 | default: |
| 157 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 158 | } |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 159 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 160 | "Nonzero MRC return value.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 161 | } |
| 162 | } else { |
| 163 | die("UEFI PEI System Agent not found.\n"); |
| 164 | } |
| 165 | |
Angel Pons | 7f454e4 | 2020-10-13 23:49:03 +0200 | [diff] [blame] | 166 | /* Print the MRC version after executing the UEFI PEI stage */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 167 | u32 version = MCHBAR32(MRC_REVISION); |
Angel Pons | 7f454e4 | 2020-10-13 23:49:03 +0200 | [diff] [blame] | 168 | printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", |
| 169 | (version >> 24) & 0xff, (version >> 16) & 0xff, |
| 170 | (version >> 8) & 0xff, (version >> 0) & 0xff); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 171 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 172 | report_memory_config(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 173 | } |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 174 | |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 175 | static uint8_t nb_get_ecc_type(const uint32_t capid0_a) |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 176 | { |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 177 | return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static uint16_t nb_slots_per_channel(const uint32_t capid0_a) |
| 181 | { |
| 182 | return !(capid0_a & CAPID_DDPCD) + 1; |
| 183 | } |
| 184 | |
| 185 | static uint16_t nb_number_of_channels(const uint32_t capid0_a) |
| 186 | { |
| 187 | return !(capid0_a & CAPID_PDCD) + 1; |
| 188 | } |
| 189 | |
| 190 | static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) |
| 191 | { |
| 192 | uint32_t ddrsz; |
| 193 | |
| 194 | /* Values from documentation, which assume two DIMMs per channel */ |
| 195 | switch (CAPID_DDRSZ(capid0_a)) { |
| 196 | case 1: |
| 197 | ddrsz = 8192; |
| 198 | break; |
| 199 | case 2: |
| 200 | ddrsz = 2048; |
| 201 | break; |
| 202 | case 3: |
| 203 | ddrsz = 512; |
| 204 | break; |
| 205 | default: |
| 206 | ddrsz = 16384; |
| 207 | break; |
| 208 | } |
| 209 | |
| 210 | /* Account for the maximum number of DIMMs per channel */ |
| 211 | return (ddrsz / 2) * nb_slots_per_channel(capid0_a); |
| 212 | } |
| 213 | |
Angel Pons | d99b693 | 2021-03-12 17:37:42 +0100 | [diff] [blame^] | 214 | static void setup_sdram_meminfo(struct pei_data *pei_data) |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 215 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 216 | struct memory_info *mem_info; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 217 | struct dimm_info *dimm; |
Angel Pons | 82654b3 | 2020-10-13 21:45:45 +0200 | [diff] [blame] | 218 | int ch, d_num; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 219 | int dimm_cnt = 0; |
| 220 | |
| 221 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); |
Nico Huber | acac02d | 2017-06-20 14:49:04 +0200 | [diff] [blame] | 222 | if (!mem_info) |
| 223 | die("Failed to add memory info to CBMEM.\n"); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 224 | |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 225 | memset(mem_info, 0, sizeof(struct memory_info)); |
| 226 | |
Angel Pons | 82654b3 | 2020-10-13 21:45:45 +0200 | [diff] [blame] | 227 | const u32 ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 228 | |
Angel Pons | 82654b3 | 2020-10-13 21:45:45 +0200 | [diff] [blame] | 229 | for (ch = 0; ch < NUM_CHANNELS; ch++) { |
| 230 | const u32 ch_conf = MCHBAR32(MAD_DIMM(ch)); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 231 | /* DIMMs A/B */ |
Angel Pons | 82654b3 | 2020-10-13 21:45:45 +0200 | [diff] [blame] | 232 | for (d_num = 0; d_num < NUM_SLOTS; d_num++) { |
| 233 | const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 234 | if (dimm_size) { |
Angel Pons | afc6c0a | 2021-03-12 15:49:55 +0100 | [diff] [blame] | 235 | const int index = ch * NUM_SLOTS + d_num; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 236 | dimm = &mem_info->dimm[dimm_cnt]; |
| 237 | dimm->dimm_size = dimm_size; |
| 238 | dimm->ddr_type = MEMORY_TYPE_DDR3; |
| 239 | dimm->ddr_frequency = ddr_frequency; |
| 240 | dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); |
| 241 | dimm->channel_num = ch; |
| 242 | dimm->dimm_num = d_num; |
| 243 | dimm->bank_locator = ch * 2; |
| 244 | memcpy(dimm->serial, |
Angel Pons | afc6c0a | 2021-03-12 15:49:55 +0100 | [diff] [blame] | 245 | &pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM], |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 246 | SPD_DIMM_SERIAL_LEN); |
| 247 | memcpy(dimm->module_part_number, |
Angel Pons | afc6c0a | 2021-03-12 15:49:55 +0100 | [diff] [blame] | 248 | &pei_data->spd_data[index][SPD_DIMM_PART_NUM], |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 249 | SPD_DIMM_PART_LEN); |
| 250 | dimm->mod_id = |
Angel Pons | afc6c0a | 2021-03-12 15:49:55 +0100 | [diff] [blame] | 251 | (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) | |
| 252 | (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 253 | dimm->mod_type = SPD_SODIMM; |
Elyes HAOUAS | 7d964ae | 2020-07-19 09:19:59 +0200 | [diff] [blame] | 254 | dimm->bus_width = MEMORY_BUS_WIDTH_64; |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 255 | dimm_cnt++; |
| 256 | } |
| 257 | } |
| 258 | } |
| 259 | mem_info->dimm_cnt = dimm_cnt; |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 260 | |
| 261 | const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 262 | |
| 263 | const uint16_t channels = nb_number_of_channels(capid0_a); |
| 264 | |
Angel Pons | 6724ba4 | 2021-01-31 15:06:59 +0100 | [diff] [blame] | 265 | mem_info->ecc_type = nb_get_ecc_type(capid0_a); |
Patrick Rudolph | 42609d8 | 2020-07-27 16:23:36 +0200 | [diff] [blame] | 266 | mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); |
| 267 | mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 268 | } |
Angel Pons | d99b693 | 2021-03-12 17:37:42 +0100 | [diff] [blame^] | 269 | |
| 270 | /* Copy SPD data for on-board memory */ |
| 271 | static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi) |
| 272 | { |
| 273 | if (!CONFIG(HAVE_SPD_IN_CBFS)) |
| 274 | return; |
| 275 | |
| 276 | printk(BIOS_DEBUG, "SPD index %d\n", spdi->spd_index); |
| 277 | |
| 278 | size_t spd_file_len; |
| 279 | uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len); |
| 280 | |
| 281 | if (!spd_file) |
| 282 | die("SPD data not found."); |
| 283 | |
| 284 | if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) { |
| 285 | printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); |
| 286 | spdi->spd_index = 0; |
| 287 | } |
| 288 | |
| 289 | if (spd_file_len < SPD_LEN) |
| 290 | die("Missing SPD data."); |
| 291 | |
| 292 | /* MRC only uses index 0, but coreboot uses the other indices */ |
| 293 | memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN); |
| 294 | |
| 295 | for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) { |
| 296 | if (spdi->addresses[i] == SPD_MEMORY_DOWN) |
| 297 | memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN); |
| 298 | } |
| 299 | } |
| 300 | |
| 301 | /* |
| 302 | * 0 = leave channel enabled |
| 303 | * 1 = disable dimm 0 on channel |
| 304 | * 2 = disable dimm 1 on channel |
| 305 | * 3 = disable dimm 0+1 on channel |
| 306 | */ |
| 307 | static int make_channel_disabled_mask(const struct pei_data *pd, int ch) |
| 308 | { |
| 309 | return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1); |
| 310 | } |
| 311 | |
| 312 | void perform_raminit(const int s3resume) |
| 313 | { |
| 314 | const struct device *gbe = pcidev_on_root(0x19, 0); |
| 315 | |
| 316 | const struct northbridge_intel_haswell_config *cfg = config_of_soc(); |
| 317 | |
| 318 | struct pei_data pei_data = { |
| 319 | .pei_version = PEI_VERSION, |
| 320 | .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, |
| 321 | .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, |
| 322 | .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, |
| 323 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 324 | .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, |
| 325 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 326 | .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, |
| 327 | .pmbase = DEFAULT_PMBASE, |
| 328 | .gpiobase = DEFAULT_GPIOBASE, |
| 329 | .temp_mmio_base = 0xfed08000, |
| 330 | .system_type = get_pch_platform_type(), |
| 331 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 332 | .ec_present = cfg->ec_present, |
| 333 | .gbe_enable = gbe && gbe->enabled, |
| 334 | .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), |
| 335 | .dq_pins_interleaved = cfg->dq_pins_interleaved, |
| 336 | .max_ddr3_freq = 1600, |
| 337 | .usb_xhci_on_resume = cfg->usb_xhci_on_resume, |
| 338 | }; |
| 339 | |
| 340 | memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports)); |
| 341 | memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports)); |
| 342 | |
| 343 | /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ |
| 344 | pei_data.boot_mode = s3resume ? 2 : 0; |
| 345 | |
| 346 | /* Obtain the SPD addresses from mainboard code */ |
| 347 | struct spd_info spdi = {0}; |
| 348 | mb_get_spd_map(&spdi); |
| 349 | |
| 350 | for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) |
| 351 | pei_data.spd_addresses[i] = spdi.addresses[i]; |
| 352 | |
| 353 | /* Calculate unimplemented DIMM slots for each channel */ |
| 354 | pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); |
| 355 | pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); |
| 356 | |
| 357 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 358 | |
| 359 | copy_spd(&pei_data, &spdi); |
| 360 | |
| 361 | sdram_initialize(&pei_data); |
| 362 | |
| 363 | timestamp_add_now(TS_AFTER_INITRAM); |
| 364 | |
| 365 | post_code(0x3b); |
| 366 | |
| 367 | intel_early_me_status(); |
| 368 | |
| 369 | int cbmem_was_initted = !cbmem_recovery(s3resume); |
| 370 | if (s3resume && !cbmem_was_initted) { |
| 371 | /* Failed S3 resume, reset to come up cleanly */ |
| 372 | printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); |
| 373 | system_reset(); |
| 374 | } |
| 375 | |
| 376 | /* Save data returned from MRC on non-S3 resumes. */ |
| 377 | if (!s3resume) |
| 378 | save_mrc_data(&pei_data); |
| 379 | |
| 380 | setup_sdram_meminfo(&pei_data); |
| 381 | } |