Angel Pons | c3f58f6 | 2020-04-05 15:46:41 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 3 | |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 4 | #include <soc/iomap.h> |
| 5 | #include <soc/irq.h> |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 6 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 7 | Scope(\) |
| 8 | { |
| 9 | // IO-Trap at 0x800. This is the ACPI->SMI communication interface. |
| 10 | |
| 11 | OperationRegion(IO_T, SystemIO, 0x800, 0x10) |
| 12 | Field(IO_T, ByteAcc, NoLock, Preserve) |
| 13 | { |
| 14 | Offset(0x8), |
| 15 | TRP0, 8 // IO-Trap at 0x808 |
| 16 | } |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 17 | |
| 18 | // Intel Legacy Block |
| 19 | OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
| 20 | Field (ILBS, AnyAcc, NoLock, Preserve) |
| 21 | { |
| 22 | Offset (0x8), |
| 23 | PRTA, 8, |
| 24 | PRTB, 8, |
| 25 | PRTC, 8, |
| 26 | PRTD, 8, |
| 27 | PRTE, 8, |
| 28 | PRTF, 8, |
| 29 | PRTG, 8, |
| 30 | PRTH, 8, |
| 31 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 32 | } |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 33 | |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 34 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 35 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 36 | |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 37 | Name(_BBN, 0) |
| 38 | |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 39 | Name (MCRS, ResourceTemplate() |
| 40 | { |
| 41 | // Bus Numbers |
| 42 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 43 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 44 | |
| 45 | // IO Region 0 |
| 46 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 47 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 48 | |
| 49 | // PCI Config Space |
| 50 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 51 | |
| 52 | // IO Region 1 |
| 53 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 54 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 55 | |
| 56 | // VGA memory (0xa0000-0xbffff) |
| 57 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 58 | Cacheable, ReadWrite, |
| 59 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 60 | 0x00020000,,, ASEG) |
| 61 | |
| 62 | // OPROM reserved (0xc0000-0xc3fff) |
| 63 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 64 | Cacheable, ReadWrite, |
| 65 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 66 | 0x00004000,,, OPR0) |
| 67 | |
| 68 | // OPROM reserved (0xc4000-0xc7fff) |
| 69 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 70 | Cacheable, ReadWrite, |
| 71 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 72 | 0x00004000,,, OPR1) |
| 73 | |
| 74 | // OPROM reserved (0xc8000-0xcbfff) |
| 75 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 76 | Cacheable, ReadWrite, |
| 77 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 78 | 0x00004000,,, OPR2) |
| 79 | |
| 80 | // OPROM reserved (0xcc000-0xcffff) |
| 81 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 82 | Cacheable, ReadWrite, |
| 83 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 84 | 0x00004000,,, OPR3) |
| 85 | |
| 86 | // OPROM reserved (0xd0000-0xd3fff) |
| 87 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 88 | Cacheable, ReadWrite, |
| 89 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 90 | 0x00004000,,, OPR4) |
| 91 | |
| 92 | // OPROM reserved (0xd4000-0xd7fff) |
| 93 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 94 | Cacheable, ReadWrite, |
| 95 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 96 | 0x00004000,,, OPR5) |
| 97 | |
| 98 | // OPROM reserved (0xd8000-0xdbfff) |
| 99 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 100 | Cacheable, ReadWrite, |
| 101 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 102 | 0x00004000,,, OPR6) |
| 103 | |
| 104 | // OPROM reserved (0xdc000-0xdffff) |
| 105 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 106 | Cacheable, ReadWrite, |
| 107 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 108 | 0x00004000,,, OPR7) |
| 109 | |
| 110 | // BIOS Extension (0xe0000-0xe3fff) |
| 111 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 112 | Cacheable, ReadWrite, |
| 113 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 114 | 0x00004000,,, ESG0) |
| 115 | |
| 116 | // BIOS Extension (0xe4000-0xe7fff) |
| 117 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 118 | Cacheable, ReadWrite, |
| 119 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 120 | 0x00004000,,, ESG1) |
| 121 | |
| 122 | // BIOS Extension (0xe8000-0xebfff) |
| 123 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 124 | Cacheable, ReadWrite, |
| 125 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 126 | 0x00004000,,, ESG2) |
| 127 | |
| 128 | // BIOS Extension (0xec000-0xeffff) |
| 129 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 130 | Cacheable, ReadWrite, |
| 131 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 132 | 0x00004000,,, ESG3) |
| 133 | |
| 134 | // System BIOS (0xf0000-0xfffff) |
| 135 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 136 | Cacheable, ReadWrite, |
| 137 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 138 | 0x00010000,,, FSEG) |
| 139 | |
| 140 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 141 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 142 | Cacheable, ReadWrite, |
| 143 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 144 | 0x00000000,,, PMEM) |
| 145 | |
| 146 | // TPM Area (0xfed40000-0xfed44fff) |
| 147 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 148 | Cacheable, ReadWrite, |
| 149 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 150 | 0x00005000,,, TPMR) |
| 151 | }) |
| 152 | |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 153 | Method (_CRS, 0, Serialized) |
| 154 | { |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 155 | |
| 156 | // Update PCI resource area |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 157 | CreateDwordField(MCRS, ^PMEM._MIN, PMIN) |
| 158 | CreateDwordField(MCRS, ^PMEM._MAX, PMAX) |
| 159 | CreateDwordField(MCRS, ^PMEM._LEN, PLEN) |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 160 | |
| 161 | // TOLM is BMBOUND accessible from IOSF so is saved in NVS |
| 162 | Store (\TOLM, PMIN) |
Dave Frodin | 2eaa0d4 | 2015-04-23 06:04:46 -0600 | [diff] [blame] | 163 | Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 164 | Add (Subtract (PMAX, PMIN), 1, PLEN) |
| 165 | |
| 166 | Return (MCRS) |
| 167 | } |
| 168 | |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 169 | /* Device Resource Consumption */ |
| 170 | Device (PDRC) |
| 171 | { |
| 172 | Name (_HID, EISAID("PNP0C02")) |
| 173 | Name (_UID, 1) |
| 174 | |
| 175 | Name (PDRS, ResourceTemplate() { |
| 176 | Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) |
| 177 | Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) |
| 178 | Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 179 | Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
| 180 | Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) |
| 181 | Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) |
| 182 | Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) |
| 183 | Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 184 | }) |
| 185 | |
| 186 | // Current Resource Settings |
| 187 | Method (_CRS, 0, Serialized) |
| 188 | { |
| 189 | Return(PDRS) |
| 190 | } |
| 191 | } |
Duncan Laurie | 93966e8 | 2013-11-04 17:28:19 -0800 | [diff] [blame] | 192 | |
| 193 | Method (_OSC, 4) |
| 194 | { |
| 195 | /* Check for proper GUID */ |
| 196 | If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) |
| 197 | { |
| 198 | /* Let OS control everything */ |
| 199 | Return (Arg3) |
| 200 | } |
| 201 | Else |
| 202 | { |
| 203 | /* Unrecognized UUID */ |
| 204 | CreateDWordField (Arg3, 0, CDW1) |
| 205 | Or (CDW1, 4, CDW1) |
| 206 | Return (Arg3) |
| 207 | } |
| 208 | } |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 209 | |
Duncan Laurie | 2e65796 | 2013-12-13 16:43:11 -0800 | [diff] [blame] | 210 | /* IOSF MBI Interface for kernel access */ |
| 211 | Device (IOSF) |
| 212 | { |
| 213 | Name (_HID, "INT33BD") |
| 214 | Name (_CID, "INT33BD") |
| 215 | Name (_UID, 1) |
| 216 | |
| 217 | Name (RBUF, ResourceTemplate () |
| 218 | { |
| 219 | /* MCR / MDR / MCRX */ |
| 220 | Memory32Fixed (ReadWrite, 0, 12, RBAR) |
| 221 | }) |
| 222 | |
| 223 | Method (_CRS) |
| 224 | { |
| 225 | CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) |
| 226 | Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) |
| 227 | Return (^RBUF) |
| 228 | } |
| 229 | } |
| 230 | |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 231 | // LPC Bridge 0:1f.0 |
| 232 | #include "lpc.asl" |
| 233 | |
Duncan Laurie | 3f94a74 | 2014-01-14 14:59:28 -0800 | [diff] [blame] | 234 | // USB XHCI 0:14.0 |
| 235 | #include "xhci.asl" |
| 236 | |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 237 | // IRQ routing for each PCI device |
| 238 | #include "irqroute.asl" |
Duncan Laurie | bb0d1ea | 2013-12-03 10:00:20 -0800 | [diff] [blame] | 239 | |
Ted Kuo | 6ecaf65 | 2014-09-16 15:31:21 +0800 | [diff] [blame] | 240 | // PCI Express Ports 0:1c.x |
| 241 | #include "pcie.asl" |
| 242 | |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 243 | Scope (\_SB) |
| 244 | { |
| 245 | // GPIO Devices |
| 246 | #include "gpio.asl" |
Matt DeVillier | e34a770 | 2017-01-09 01:35:48 -0600 | [diff] [blame] | 247 | } |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 248 | |
Matt DeVillier | e34a770 | 2017-01-09 01:35:48 -0600 | [diff] [blame] | 249 | Scope (\_SB.PCI0) |
| 250 | { |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 251 | // LPSS Devices |
| 252 | #include "lpss.asl" |
| 253 | |
| 254 | // SCC Devices |
| 255 | #include "scc.asl" |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 256 | |
| 257 | // LPE Device |
| 258 | #include "lpe.asl" |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 259 | } |