Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 13 | */ |
| 14 | |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 15 | #include <cpu/x86/smm.h> |
| 16 | #include <device/device.h> |
| 17 | #include <device/pci.h> |
| 18 | #include <device/pci_ids.h> |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 19 | #include <vendorcode/google/chromeos/chromeos.h> |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Matt DeVillier | f05d2e1 | 2017-06-06 23:56:18 -0500 | [diff] [blame] | 21 | #include <stddef.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 22 | #include <soc/iomap.h> |
| 23 | #include <soc/iosf.h> |
| 24 | #include <soc/pci_devs.h> |
| 25 | #include <soc/ramstage.h> |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 26 | |
| 27 | /* Host Memory Map: |
| 28 | * |
| 29 | * +--------------------------+ BMBOUND_HI |
| 30 | * | Usable DRAM | |
| 31 | * +--------------------------+ 4GiB |
| 32 | * | PCI Address Space | |
| 33 | * +--------------------------+ BMBOUND |
| 34 | * | TPM | |
| 35 | * +--------------------------+ IMR2 |
| 36 | * | TXE | |
| 37 | * +--------------------------+ IMR1 |
| 38 | * | iGD | |
| 39 | * +--------------------------+ |
| 40 | * | GTT | |
| 41 | * +--------------------------+ SMMRRH, IRM0 |
| 42 | * | TSEG | |
| 43 | * +--------------------------+ SMMRRL |
| 44 | * | Usable DRAM | |
| 45 | * +--------------------------+ 0 |
| 46 | * |
| 47 | * Note that there are really only a few regions that need to enumerated w.r.t. |
Martin Roth | 99a3bba | 2014-12-07 14:57:26 -0700 | [diff] [blame] | 48 | * coreboot's resource model: |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 49 | * |
| 50 | * +--------------------------+ BMBOUND_HI |
| 51 | * | Cacheable/Usable | |
| 52 | * +--------------------------+ 4GiB |
| 53 | * |
| 54 | * +--------------------------+ BMBOUND |
| 55 | * | Uncacheable/Reserved | |
| 56 | * +--------------------------+ SMMRRH |
| 57 | * | Cacheable/Reserved | |
| 58 | * +--------------------------+ SMMRRL |
| 59 | * | Cacheable/Usable | |
| 60 | * +--------------------------+ 0 |
| 61 | */ |
| 62 | #define RES_IN_KiB(r) ((r) >> 10) |
| 63 | |
Duncan Laurie | 1f52f51 | 2013-11-04 17:02:45 -0800 | [diff] [blame] | 64 | uint32_t nc_read_top_of_low_memory(void) |
| 65 | { |
Kyösti Mälkki | 117cf2b | 2019-08-20 06:01:57 +0300 | [diff] [blame] | 66 | MAYBE_STATIC_BSS uint32_t tolm = 0; |
Matt DeVillier | f05d2e1 | 2017-06-06 23:56:18 -0500 | [diff] [blame] | 67 | |
| 68 | if (tolm) |
| 69 | return tolm; |
| 70 | |
| 71 | tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); |
| 72 | |
| 73 | return tolm; |
Duncan Laurie | 1f52f51 | 2013-11-04 17:02:45 -0800 | [diff] [blame] | 74 | } |
| 75 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 76 | static void nc_read_resources(struct device *dev) |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 77 | { |
| 78 | unsigned long mmconf; |
| 79 | unsigned long bmbound; |
| 80 | unsigned long bmbound_hi; |
| 81 | unsigned long smmrrh; |
| 82 | unsigned long smmrrl; |
| 83 | unsigned long base_k, size_k; |
| 84 | const unsigned long four_gig_kib = (4 << (30 - 10)); |
| 85 | int index = 0; |
| 86 | |
| 87 | /* Read standard PCI resources. */ |
| 88 | pci_dev_read_resources(dev); |
| 89 | |
| 90 | /* PCIe memory-mapped config space access - 256 MiB. */ |
| 91 | mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); |
| 92 | mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); |
| 93 | |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 94 | /* 0 -> 0xa0000 */ |
| 95 | base_k = RES_IN_KiB(0); |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 96 | size_k = RES_IN_KiB(0xa0000) - base_k; |
| 97 | ram_resource(dev, index++, base_k, size_k); |
| 98 | |
| 99 | /* The SMMRR registers are 1MiB granularity with smmrrh being |
| 100 | * inclusive of the SMM region. */ |
| 101 | smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; |
| 102 | smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; |
| 103 | |
| 104 | /* 0xc0000 -> smrrl - cacheable and usable */ |
| 105 | base_k = RES_IN_KiB(0xc0000); |
| 106 | size_k = smmrrl - base_k; |
| 107 | ram_resource(dev, index++, base_k, size_k); |
| 108 | |
| 109 | if (smmrrh > smmrrl) |
| 110 | reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); |
| 111 | |
| 112 | /* All address space between bmbound and smmrrh is unusable. */ |
Duncan Laurie | 1f52f51 | 2013-11-04 17:02:45 -0800 | [diff] [blame] | 113 | bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 114 | mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); |
| 115 | |
| 116 | /* The BMBOUND_HI register matches register bits of 31:24 with address |
| 117 | * bits of 35:28. Therefore, shift register to align properly. */ |
| 118 | bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); |
| 119 | bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; |
| 120 | if (bmbound_hi > four_gig_kib) |
| 121 | ram_resource(dev, index++, four_gig_kib, |
| 122 | bmbound_hi - four_gig_kib); |
Duncan Laurie | e7e78d6 | 2013-11-03 19:38:12 -0800 | [diff] [blame] | 123 | |
| 124 | /* Reserve everything between A segment and 1MB: |
| 125 | * |
| 126 | * 0xa0000 - 0xbffff: legacy VGA |
| 127 | * 0xc0000 - 0xfffff: RAM |
| 128 | */ |
| 129 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
| 130 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), |
| 131 | (0x100000 - 0xc0000) >> 10); |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 132 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 133 | if (CONFIG(CHROMEOS)) |
Frans Hendriks | ef05dc8 | 2018-11-27 10:35:16 +0100 | [diff] [blame] | 134 | chromeos_reserve_ram_oops(dev, index++); |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 135 | } |
| 136 | |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 137 | static struct device_operations nc_ops = { |
| 138 | .read_resources = nc_read_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 139 | .acpi_fill_ssdt = generate_cpu_entries, |
Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame] | 140 | .ops_pci = &soc_pci_ops, |
| 141 | }; |
| 142 | |
| 143 | static const struct pci_driver nc_driver __pci_driver = { |
| 144 | .ops = &nc_ops, |
| 145 | .vendor = PCI_VENDOR_ID_INTEL, |
| 146 | .device = SOC_DEVID, |
| 147 | }; |