Aaron Durbin | 191570d | 2013-09-24 12:41:08 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <cpu/x86/smm.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | |
| 26 | #include <baytrail/iosf.h> |
| 27 | #include <baytrail/pci_devs.h> |
| 28 | #include <baytrail/ramstage.h> |
| 29 | |
| 30 | /* Host Memory Map: |
| 31 | * |
| 32 | * +--------------------------+ BMBOUND_HI |
| 33 | * | Usable DRAM | |
| 34 | * +--------------------------+ 4GiB |
| 35 | * | PCI Address Space | |
| 36 | * +--------------------------+ BMBOUND |
| 37 | * | TPM | |
| 38 | * +--------------------------+ IMR2 |
| 39 | * | TXE | |
| 40 | * +--------------------------+ IMR1 |
| 41 | * | iGD | |
| 42 | * +--------------------------+ |
| 43 | * | GTT | |
| 44 | * +--------------------------+ SMMRRH, IRM0 |
| 45 | * | TSEG | |
| 46 | * +--------------------------+ SMMRRL |
| 47 | * | Usable DRAM | |
| 48 | * +--------------------------+ 0 |
| 49 | * |
| 50 | * Note that there are really only a few regions that need to enumerated w.r.t. |
| 51 | * coreboot's resrouce model: |
| 52 | * |
| 53 | * +--------------------------+ BMBOUND_HI |
| 54 | * | Cacheable/Usable | |
| 55 | * +--------------------------+ 4GiB |
| 56 | * |
| 57 | * +--------------------------+ BMBOUND |
| 58 | * | Uncacheable/Reserved | |
| 59 | * +--------------------------+ SMMRRH |
| 60 | * | Cacheable/Reserved | |
| 61 | * +--------------------------+ SMMRRL |
| 62 | * | Cacheable/Usable | |
| 63 | * +--------------------------+ 0 |
| 64 | */ |
| 65 | #define RES_IN_KiB(r) ((r) >> 10) |
| 66 | |
| 67 | static void soc_trans_router_read_resources(device_t dev) |
| 68 | { |
| 69 | unsigned long mmconf; |
| 70 | unsigned long bmbound; |
| 71 | unsigned long bmbound_hi; |
| 72 | unsigned long smmrrh; |
| 73 | unsigned long smmrrl; |
| 74 | unsigned long base_k, size_k; |
| 75 | const unsigned long four_gig_kib = (4 << (30 - 10)); |
| 76 | int index = 0; |
| 77 | |
| 78 | /* Read standard PCI resources. */ |
| 79 | pci_dev_read_resources(dev); |
| 80 | |
| 81 | /* PCIe memory-mapped config space access - 256 MiB. */ |
| 82 | mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); |
| 83 | mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); |
| 84 | |
| 85 | /* 0 -> SMM_DEFAULT_BASE cacheable ram. */ |
| 86 | ram_resource(dev, index++, 0, RES_IN_KiB(SMM_DEFAULT_BASE)); |
| 87 | /* Default SMM region is cacheable but reserved for coreboot */ |
| 88 | reserved_ram_resource(dev, index++, RES_IN_KiB(SMM_DEFAULT_BASE), |
| 89 | RES_IN_KiB(SMM_DEFAULT_SIZE)); |
| 90 | |
| 91 | /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE - > 0xa0000 */ |
| 92 | base_k = RES_IN_KiB(SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE); |
| 93 | size_k = RES_IN_KiB(0xa0000) - base_k; |
| 94 | ram_resource(dev, index++, base_k, size_k); |
| 95 | |
| 96 | /* The SMMRR registers are 1MiB granularity with smmrrh being |
| 97 | * inclusive of the SMM region. */ |
| 98 | smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; |
| 99 | smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; |
| 100 | |
| 101 | /* 0xc0000 -> smrrl - cacheable and usable */ |
| 102 | base_k = RES_IN_KiB(0xc0000); |
| 103 | size_k = smmrrl - base_k; |
| 104 | ram_resource(dev, index++, base_k, size_k); |
| 105 | |
| 106 | if (smmrrh > smmrrl) |
| 107 | reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); |
| 108 | |
| 109 | /* All address space between bmbound and smmrrh is unusable. */ |
| 110 | bmbound = RES_IN_KiB(iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1)); |
| 111 | mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); |
| 112 | |
| 113 | /* The BMBOUND_HI register matches register bits of 31:24 with address |
| 114 | * bits of 35:28. Therefore, shift register to align properly. */ |
| 115 | bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); |
| 116 | bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; |
| 117 | if (bmbound_hi > four_gig_kib) |
| 118 | ram_resource(dev, index++, four_gig_kib, |
| 119 | bmbound_hi - four_gig_kib); |
| 120 | } |
| 121 | |
| 122 | static void nc_read_resources(device_t dev) |
| 123 | { |
| 124 | /* For some reason the graphics pci device (0, 2, 0) and the SoC |
| 125 | * transaction router are coming up with the same device id. */ |
| 126 | if (dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)) == dev) |
| 127 | return soc_trans_router_read_resources(dev); |
| 128 | else |
| 129 | /* Read standard PCI resources. */ |
| 130 | pci_dev_read_resources(dev); |
| 131 | |
| 132 | } |
| 133 | |
| 134 | static struct device_operations nc_ops = { |
| 135 | .read_resources = nc_read_resources, |
| 136 | .set_resources = NULL, |
| 137 | .enable_resources = NULL, |
| 138 | .init = NULL, |
| 139 | .enable = NULL, |
| 140 | .scan_bus = NULL, |
| 141 | .ops_pci = &soc_pci_ops, |
| 142 | }; |
| 143 | |
| 144 | static const struct pci_driver nc_driver __pci_driver = { |
| 145 | .ops = &nc_ops, |
| 146 | .vendor = PCI_VENDOR_ID_INTEL, |
| 147 | .device = SOC_DEVID, |
| 148 | }; |
| 149 | |