Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | 6fcee75 | 2021-02-14 15:06:50 +0200 | [diff] [blame] | 3 | #include <assert.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 4 | #include <bootblock_common.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 5 | #include <device/pci.h> |
Kyösti Mälkki | 6fcee75 | 2021-02-14 15:06:50 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 7 | #include <FsptUpd.h> |
| 8 | #include <intelblocks/fast_spi.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 9 | #include <soc/bootblock.h> |
Kyösti Mälkki | 6fcee75 | 2021-02-14 15:06:50 +0200 | [diff] [blame] | 10 | #include <soc/pci_devs.h> |
| 11 | #include <soc/systemagent.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 12 | #include <spi-generic.h> |
Kyösti Mälkki | 6fcee75 | 2021-02-14 15:06:50 +0200 | [diff] [blame] | 13 | #include <stdint.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 14 | #include <console/console.h> |
| 15 | |
| 16 | const FSPT_UPD temp_ram_init_params = { |
| 17 | .FspUpdHeader = { |
| 18 | .Signature = 0x545F445055564E44ULL, |
| 19 | .Revision = 1, |
| 20 | .Reserved = {0}, |
| 21 | }, |
| 22 | .FsptCoreUpd = { |
Subrata Banik | 24ab1c5 | 2019-11-25 11:57:28 +0530 | [diff] [blame] | 23 | /* |
| 24 | * It is a requirement for firmware to have Firmware Interface Table |
| 25 | * (FIT), which contains pointers to each microcode update. |
| 26 | * The microcode update is loaded for all logical processors before |
| 27 | * cpu reset vector. |
| 28 | * |
| 29 | * All SoC since Gen-4 has above mechanism in place to load microcode |
| 30 | * even before hitting CPU reset vector. Hence skipping FSP-T loading |
| 31 | * microcode after CPU reset by passing '0' value to |
| 32 | * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. |
| 33 | */ |
| 34 | .MicrocodeRegionBase = 0, |
| 35 | .MicrocodeRegionLength = 0, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 36 | .CodeRegionBase = |
Arthur Heymans | 62c0b61 | 2019-02-05 21:10:01 +0100 | [diff] [blame] | 37 | (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), |
| 38 | .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 39 | .Reserved1 = {0}, |
| 40 | }, |
| 41 | .FsptConfig = { |
| 42 | .PcdFsptPort80RouteDisable = 0, |
| 43 | .ReservedTempRamInitUpd = {0}, |
| 44 | }, |
| 45 | .UnusedUpdSpace0 = {0}, |
| 46 | .UpdTerminator = 0x55AA, |
| 47 | }; |
| 48 | |
| 49 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
| 50 | { |
| 51 | /* Call lib/bootblock.c main */ |
Kyösti Mälkki | 101ef0b | 2019-08-18 06:58:42 +0300 | [diff] [blame] | 52 | bootblock_main_with_basetime(base_timestamp); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 53 | }; |
| 54 | |
Kyösti Mälkki | 6fcee75 | 2021-02-14 15:06:50 +0200 | [diff] [blame] | 55 | static void sanity_check_pci_mmconf(void) |
| 56 | { |
| 57 | u32 pciexbar, base = 0, length = 0; |
| 58 | |
| 59 | pciexbar = pci_io_read_config32(PCH_SA_DEV, PCIEXBAR); |
| 60 | assert(pciexbar & (1 << 0)); |
| 61 | |
| 62 | switch (pciexbar & MASK_PCIEXBAR_LENGTH) { |
| 63 | case MASK_PCIEXBAR_LENGTH_256M: |
| 64 | base = pciexbar & MASK_PCIEXBAR_256M; |
| 65 | length = 256; |
| 66 | break; |
| 67 | case MASK_PCIEXBAR_LENGTH_128M: |
| 68 | base = pciexbar & MASK_PCIEXBAR_128M; |
| 69 | length = 128; |
| 70 | break; |
| 71 | case MASK_PCIEXBAR_LENGTH_64M: |
| 72 | base = pciexbar & MASK_PCIEXBAR_64M; |
| 73 | length = 64; |
| 74 | break; |
| 75 | } |
| 76 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 77 | assert(base == CONFIG_ECAM_MMCONF_BASE_ADDRESS); |
| 78 | assert(length == CONFIG_ECAM_MMCONF_BUS_NUMBER); |
Kyösti Mälkki | 6fcee75 | 2021-02-14 15:06:50 +0200 | [diff] [blame] | 79 | } |
| 80 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 81 | void bootblock_soc_early_init(void) |
| 82 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 83 | #if (CONFIG(CONSOLE_SERIAL)) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 84 | early_uart_init(); |
| 85 | #endif |
Kyösti Mälkki | 3990da0 | 2021-11-15 17:25:54 +0200 | [diff] [blame] | 86 | fast_spi_early_init(DEFAULT_SPI_BASE); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 87 | }; |
| 88 | |
| 89 | void bootblock_soc_init(void) |
| 90 | { |
Kyösti Mälkki | 6fcee75 | 2021-02-14 15:06:50 +0200 | [diff] [blame] | 91 | sanity_check_pci_mmconf(); |
| 92 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 93 | if (CONFIG(BOOTBLOCK_CONSOLE)) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 94 | printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); |
| 95 | }; |