Angel Pons | 32859fc | 2020-04-02 23:48:27 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 2 | |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 3 | /* This file applies to AMD64 products. |
| 4 | * The definitions come from the AMD64 Programmers Manual vol2 |
| 5 | * Revision 3.30 and/or the device's BKDG. |
| 6 | */ |
| 7 | |
Stefan Reinauer | 991f184 | 2015-11-22 23:40:29 +0100 | [diff] [blame] | 8 | #ifndef CPU_AMD_MSR_H |
| 9 | #define CPU_AMD_MSR_H |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 10 | |
Patrick Georgi | 3d5bb23 | 2010-05-09 21:15:13 +0000 | [diff] [blame] | 11 | #include <cpu/x86/msr.h> |
| 12 | |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 13 | #define MC4_MISC0 0x00000413 |
| 14 | #define MC4_MISC1 0xC0000408 |
| 15 | #define MC4_MISC2 0xC0000409 |
| 16 | #define FS_Base 0xC0000100 |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 17 | #define HWCR_MSR 0xC0010015 |
Felix Held | 357cc65 | 2020-07-09 00:04:22 +0200 | [diff] [blame] | 18 | #define SMM_LOCK (1 << 0) |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 19 | #define NB_CFG_MSR 0xC001001f |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 20 | #define FidVidStatus 0xC0010042 |
Felix Held | 4f51c94 | 2021-07-13 02:39:09 +0200 | [diff] [blame] | 21 | #define MC0_CTL_MASK 0xC0010044 |
Felix Held | 71b918d | 2021-07-13 18:31:40 +0200 | [diff] [blame] | 22 | #define MC_CTL_MASK(bank) (MC0_CTL_MASK + (bank)) |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 23 | #define MSR_INTPEND 0xC0010055 |
| 24 | #define MMIO_CONF_BASE 0xC0010058 |
| 25 | #define MMIO_RANGE_EN (1 << 0) |
Marshall Dawson | 914e6b4 | 2019-07-01 09:56:12 -0500 | [diff] [blame] | 26 | #define MMIO_BUS_RANGE_SHIFT 2 |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 27 | /* P-state Current Limit Register */ |
| 28 | #define PS_LIM_REG 0xC0010061 |
| 29 | /* P-state Maximum Value shift position */ |
| 30 | #define PS_MAX_VAL_SHFT 4 |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 31 | #define PS_LIM_MAX_VAL_MASK (0x7 << PS_MAX_VAL_SHFT) |
| 32 | #define MAX_PSTATES 8 |
| 33 | |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 34 | /* P-state Control Register */ |
| 35 | #define PS_CTL_REG 0xC0010062 |
| 36 | /* P-state Control Register CMD Mask OFF */ |
| 37 | #define PS_CMD_MASK_OFF ~(7) |
| 38 | /* P-state Status Mask */ |
| 39 | #define PS_STS_MASK 7 |
| 40 | /* P-state Status Register */ |
| 41 | #define PS_STS_REG 0xC0010063 |
| 42 | #define PSTATE_0_MSR 0xC0010064 |
Felix Held | 0a46604 | 2023-02-27 23:56:39 +0100 | [diff] [blame] | 43 | #define PSTATE_MSR(pstate) (PSTATE_0_MSR + (pstate)) |
Felix Held | c04d3ddb | 2023-07-17 22:59:02 +0200 | [diff] [blame^] | 44 | #define PSTATE_MSR_COUNT 8 |
Felix Held | 78633e3 | 2023-03-07 03:08:27 +0100 | [diff] [blame] | 45 | |
Elyes HAOUAS | 1a5f1c8 | 2018-10-31 08:06:12 +0100 | [diff] [blame] | 46 | #define MSR_PATCH_LOADER 0xC0010020 |
| 47 | |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 48 | #define MSR_COFVID_STS 0xC0010071 |
| 49 | #define MSR_CSTATE_ADDRESS 0xC0010073 |
Jason Glenesk | bc52143 | 2020-09-14 05:22:47 -0700 | [diff] [blame] | 50 | #define MSR_CSTATE_ADDRESS_MASK 0xFFFF |
| 51 | |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 52 | #define OSVW_ID_Length 0xC0010140 |
| 53 | #define OSVW_Status 0xC0010141 |
| 54 | |
Rudolf Marek | b5b3b3b | 2011-07-02 16:36:17 +0200 | [diff] [blame] | 55 | #define SMM_BASE_MSR 0xC0010111 |
| 56 | #define SMM_ADDR_MSR 0xC0010112 |
| 57 | #define SMM_MASK_MSR 0xC0010113 |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 58 | #define SMM_TSEG_VALID (1 << 1) |
| 59 | #define SMM_TSEG_WB (6 << 12) |
Rudolf Marek | b5b3b3b | 2011-07-02 16:36:17 +0200 | [diff] [blame] | 60 | |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 61 | #define CPU_ID_FEATURES_MSR 0xC0011004 |
| 62 | #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 |
| 63 | #define CPU_ID_HYPER_EXT_FEATURES 0xC001100d |
| 64 | #define LOGICAL_CPUS_NUM_MSR 0xC001100d |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 65 | #define LS_CFG_MSR 0xC0011020 |
| 66 | #define IC_CFG_MSR 0xC0011021 |
| 67 | #define DC_CFG_MSR 0xC0011022 |
| 68 | #define BU_CFG_MSR 0xC0011023 |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 69 | #define FP_CFG_MSR 0xC0011028 |
| 70 | #define DE_CFG_MSR 0xC0011029 |
Marco Schmidt | c263b44 | 2009-06-06 11:21:52 +0000 | [diff] [blame] | 71 | #define BU_CFG2_MSR 0xC001102A |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 72 | #define BU_CFG3_MSR 0xC001102B |
| 73 | #define EX_CFG_MSR 0xC001102C |
| 74 | #define LS_CFG2_MSR 0xC001102D |
| 75 | #define IBS_OP_DATA3_MSR 0xC0011037 |
Raul E Rangel | ec26428 | 2020-06-04 16:42:50 -0600 | [diff] [blame] | 76 | #define S3_RESUME_EIP_MSR 0xC00110E0 |
Felix Held | e09294f | 2021-02-17 22:22:21 +0100 | [diff] [blame] | 77 | #define PSP_ADDR_MSR 0xc00110a2 |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 78 | |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 79 | #define CORE_PERF_BOOST_CTRL 0x15c |
Marc Jones | 8ae8c88 | 2007-12-19 01:32:08 +0000 | [diff] [blame] | 80 | |
Stefan Reinauer | 991f184 | 2015-11-22 23:40:29 +0100 | [diff] [blame] | 81 | #endif /* CPU_AMD_MSR_H */ |