Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 1 | chip soc/intel/alderlake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 7 | # GPE configuration |
| 8 | # Note that GPE events called out in ASL code rely on this |
| 9 | # route. i.e. If this route changes then the affected GPE |
| 10 | # offset bits also need to be changed. |
| 11 | register "pmc_gpe0_dw0" = "GPP_B" |
| 12 | register "pmc_gpe0_dw1" = "GPP_D" |
| 13 | register "pmc_gpe0_dw2" = "GPP_E" |
| 14 | |
Sridhar Siricilla | edc6da2 | 2021-04-07 10:18:43 +0530 | [diff] [blame] | 15 | # Enable HECI1 interface |
| 16 | register "HeciEnabled" = "1" |
| 17 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 18 | # FSP configuration |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 19 | |
Cliff Huang | b1a128f | 2021-02-10 18:07:46 -0800 | [diff] [blame] | 20 | # Enable CNVi BT |
| 21 | register "CnviBtCore" = "true" |
| 22 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 23 | register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 |
| 24 | register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 |
| 25 | register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 |
| 26 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
| 27 | register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 |
| 28 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector |
| 29 | register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 |
| 30 | register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 |
| 31 | register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 |
| 32 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN |
| 33 | |
| 34 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 |
| 35 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 |
| 36 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 |
| 37 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN |
| 38 | |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 39 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 40 | register "gen1_dec" = "0x00fc0801" |
| 41 | register "gen2_dec" = "0x000c0201" |
| 42 | # EC memory map range is 0x900-0x9ff |
| 43 | register "gen3_dec" = "0x00fc0901" |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 44 | |
Subrata Banik | f965077 | 2021-03-24 16:49:14 +0530 | [diff] [blame] | 45 | # This disabled autonomous GPIO power management, otherwise |
| 46 | # old cr50 FW only supports short pulses; need to clarify |
| 47 | # the minimum PCH IRQ pulse width with Intel, b/180111628 |
| 48 | register "gpio_override_pm" = "1" |
| 49 | register "gpio_pm[COMM_0]" = "0" |
| 50 | register "gpio_pm[COMM_1]" = "0" |
| 51 | register "gpio_pm[COMM_2]" = "0" |
| 52 | register "gpio_pm[COMM_4]" = "0" |
| 53 | register "gpio_pm[COMM_5]" = "0" |
| 54 | |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 55 | # Enable PCH PCIE RP 5 using CLK 2 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 56 | register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| 57 | .clk_src = 2, |
| 58 | .clk_req = 2, |
| 59 | .flags = PCIE_RP_CLK_REQ_DETECT, |
| 60 | }" |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 61 | |
| 62 | # Enable PCH PCIE RP 6 using CLK 5 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 63 | register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| 64 | .clk_src = 5, |
| 65 | .clk_req = 5, |
| 66 | .flags = PCIE_RP_CLK_REQ_DETECT, |
| 67 | }" |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 68 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 69 | # Enable PCH PCIE RP 8 using free running CLK (0x80) |
| 70 | # Clock source is shared with LAN and hence marked as free running. |
| 71 | register "pch_pcie_rp[PCH_RP(8)]" = "{ |
| 72 | .flags = PCIE_RP_CLK_SRC_UNUSED, |
| 73 | }" |
| 74 | register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" |
Subrata Banik | 840679d | 2020-11-27 00:46:18 +0530 | [diff] [blame] | 75 | |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 76 | # Enable PCH PCIE RP 9 using CLK 1 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 77 | register "pch_pcie_rp[PCH_RP(9)]" = "{ |
| 78 | .clk_src = 1, |
| 79 | .clk_req = 1, |
| 80 | .flags = PCIE_RP_CLK_REQ_DETECT, |
| 81 | }" |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 82 | |
Subrata Banik | 6147314 | 2020-10-14 22:06:48 +0530 | [diff] [blame] | 83 | # Enable PCH PCIE RP 11 for optane |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 84 | register "pch_pcie_rp[PCH_RP(11)]" = "{ |
| 85 | .flags = PCIE_RP_CLK_SRC_UNUSED, |
| 86 | }" |
| 87 | |
Subrata Banik | 3f561a8 | 2020-10-14 22:12:12 +0530 | [diff] [blame] | 88 | # Hybrid storage mode |
| 89 | register "HybridStorageMode" = "1" |
Subrata Banik | 6147314 | 2020-10-14 22:06:48 +0530 | [diff] [blame] | 90 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 91 | # Enable CPU PCIE RP 1 using CLK 0 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 92 | register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| 93 | .clk_req = 0, |
| 94 | .clk_src = 0, |
| 95 | }" |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 96 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 97 | # Enable CPU PCIE RP 2 using CLK 3 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 98 | register "cpu_pcie_rp[CPU_RP(2)]" = "{ |
| 99 | .clk_req = 3, |
| 100 | .clk_src = 3, |
| 101 | }" |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 102 | |
| 103 | # Enable CPU PCIE RP 3 using CLK 4 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 104 | register "cpu_pcie_rp[CPU_RP(3)]" = "{ |
| 105 | .clk_req = 4, |
| 106 | .clk_src = 4, |
| 107 | }" |
Subrata Banik | 8c4aa15 | 2021-01-09 16:38:34 +0530 | [diff] [blame] | 108 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 109 | register "SataSalpSupport" = "1" |
| 110 | |
| 111 | register "SataPortsEnable" = "{ |
Subrata Banik | 1d18c8e | 2021-01-29 19:05:30 +0530 | [diff] [blame] | 112 | [0] = 1, |
| 113 | [1] = 1, |
| 114 | [2] = 1, |
| 115 | [3] = 1, |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 116 | }" |
| 117 | |
| 118 | register "SataPortsDevSlp" = "{ |
Subrata Banik | 1d18c8e | 2021-01-29 19:05:30 +0530 | [diff] [blame] | 119 | [0] = 1, |
| 120 | [1] = 1, |
| 121 | [2] = 1, |
| 122 | [3] = 1, |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 123 | }" |
| 124 | |
| 125 | # Enable EDP in PortA |
| 126 | register "DdiPortAConfig" = "1" |
Subrata Banik | 8ed53ec | 2020-11-21 19:50:56 +0530 | [diff] [blame] | 127 | # Enable HDMI in Port B |
| 128 | register "DdiPortBDdc" = "1" |
| 129 | register "DdiPortBHpd" = "1" |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 130 | |
| 131 | # TCSS USB3 |
| 132 | register "TcssAuxOri" = "0" |
| 133 | |
| 134 | register "s0ix_enable" = "1" |
Sumeet R Pawnikar | eb2a784 | 2021-04-01 14:22:31 +0530 | [diff] [blame] | 135 | register "dptf_enable" = "1" |
| 136 | |
| 137 | register "power_limits_config" = "{ |
| 138 | .tdp_pl1_override = 45, |
| 139 | .tdp_pl2_override = 56, |
| 140 | }" |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 141 | |
| 142 | register "SerialIoI2cMode" = "{ |
Subrata Banik | 1d18c8e | 2021-01-29 19:05:30 +0530 | [diff] [blame] | 143 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 144 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 145 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 146 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 147 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 148 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 149 | }" |
| 150 | |
| 151 | register "SerialIoGSpiMode" = "{ |
| 152 | [PchSerialIoIndexGSPI0] = PchSerialIoPci, |
| 153 | [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| 154 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 155 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 156 | }" |
| 157 | |
| 158 | register "SerialIoGSpiCsMode" = "{ |
| 159 | [PchSerialIoIndexGSPI0] = 0, |
| 160 | [PchSerialIoIndexGSPI1] = 0, |
| 161 | [PchSerialIoIndexGSPI2] = 0, |
| 162 | [PchSerialIoIndexGSPI3] = 0, |
| 163 | }" |
| 164 | |
| 165 | register "SerialIoGSpiCsState" = "{ |
| 166 | [PchSerialIoIndexGSPI0] = 0, |
| 167 | [PchSerialIoIndexGSPI1] = 0, |
| 168 | [PchSerialIoIndexGSPI2] = 0, |
| 169 | [PchSerialIoIndexGSPI3] = 0, |
| 170 | }" |
| 171 | |
| 172 | register "SerialIoUartMode" = "{ |
| 173 | [PchSerialIoIndexUART0] = PchSerialIoSkipInit, |
| 174 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 175 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 176 | }" |
| 177 | |
| 178 | # HD Audio |
| 179 | register "PchHdaDspEnable" = "1" |
Sugnan Prabhu S | 50f8b4e | 2021-03-18 22:08:22 +0530 | [diff] [blame] | 180 | register "PchHdaIDispLinkTmode" = "HDA_TMODE_4T" |
| 181 | register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" |
| 182 | register "PchHdaIDispCodecEnable" = "1" |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 183 | |
Usha P | f02fa4a | 2021-02-23 17:56:46 +0530 | [diff] [blame] | 184 | register "CnviBtAudioOffload" = "true" |
| 185 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 186 | # Intel Common SoC Config |
| 187 | register "common_soc_config" = "{ |
| 188 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 189 | .i2c[0] = { |
| 190 | .speed = I2C_SPEED_FAST, |
| 191 | }, |
| 192 | .i2c[1] = { |
| 193 | .speed = I2C_SPEED_FAST, |
| 194 | }, |
| 195 | .i2c[2] = { |
| 196 | .speed = I2C_SPEED_FAST, |
| 197 | }, |
| 198 | .i2c[3] = { |
| 199 | .speed = I2C_SPEED_FAST, |
| 200 | }, |
| 201 | .i2c[5] = { |
| 202 | .speed = I2C_SPEED_FAST, |
| 203 | }, |
| 204 | }" |
| 205 | |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 206 | device domain 0 on |
| 207 | device pci 00.0 on end # Host Bridge |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 208 | device pci 01.0 on end # PEG10 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 209 | device pci 02.0 on end # Graphics |
Sumeet R Pawnikar | eb2a784 | 2021-04-01 14:22:31 +0530 | [diff] [blame] | 210 | device pci 04.0 on |
| 211 | chip drivers/intel/dptf |
| 212 | |
| 213 | ## sensor information |
| 214 | register "options.tsr[0].desc" = ""Ambient"" |
| 215 | register "options.tsr[1].desc" = ""Battery"" |
| 216 | register "options.tsr[2].desc" = ""DDR"" |
| 217 | register "options.tsr[3].desc" = ""Skin"" |
| 218 | |
| 219 | ## Active Policy |
| 220 | # TODO: below values are initial reference values only |
| 221 | register "policies.active" = "{ |
| 222 | [0] = { |
| 223 | .target = DPTF_CPU, |
| 224 | .thresholds = { |
| 225 | TEMP_PCT(95, 90), |
| 226 | TEMP_PCT(90, 80), |
| 227 | } |
| 228 | }, |
| 229 | [1] = { |
| 230 | .target = DPTF_TEMP_SENSOR_0, |
| 231 | .thresholds = { |
| 232 | TEMP_PCT(80, 90), |
| 233 | TEMP_PCT(70, 80), |
| 234 | } |
| 235 | } |
| 236 | }" |
| 237 | |
| 238 | ## Passive Policy |
| 239 | # TODO: below values are initial reference values only |
| 240 | register "policies.passive" = "{ |
| 241 | [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000), |
| 242 | [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000), |
| 243 | [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000), |
| 244 | [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000), |
| 245 | [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000), |
| 246 | }" |
| 247 | |
| 248 | ## Critical Policy |
| 249 | # TODO: below values are initial reference values only |
| 250 | register "policies.critical" = "{ |
| 251 | [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), |
| 252 | [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), |
| 253 | [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), |
| 254 | [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), |
| 255 | [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), |
| 256 | }" |
| 257 | |
| 258 | ## Power Limits Control |
| 259 | register "controls.power_limits" = "{ |
| 260 | .pl1 = { |
| 261 | .min_power = 35000, |
| 262 | .max_power = 45000, |
| 263 | .time_window_min = 28 * MSECS_PER_SEC, |
| 264 | .time_window_max = 32 * MSECS_PER_SEC, |
| 265 | .granularity = 200, |
| 266 | }, |
| 267 | .pl2 = { |
| 268 | .min_power = 56000, |
| 269 | .max_power = 56000, |
| 270 | .time_window_min = 28 * MSECS_PER_SEC, |
| 271 | .time_window_max = 32 * MSECS_PER_SEC, |
| 272 | .granularity = 1000, |
| 273 | } |
| 274 | }" |
| 275 | |
| 276 | ## Charger Performance Control (Control, mA) |
| 277 | register "controls.charger_perf" = "{ |
| 278 | [0] = { 255, 3000 }, |
| 279 | [1] = { 24, 1500 }, |
| 280 | [2] = { 16, 1000 }, |
| 281 | [3] = { 8, 500 } |
| 282 | }" |
| 283 | |
| 284 | ## Fan Performance Control (Percent, Speed, Noise, Power) |
| 285 | register "controls.fan_perf" = "{ |
| 286 | [0] = { 90, 6700, 220, 2200, }, |
| 287 | [1] = { 80, 5800, 180, 1800, }, |
| 288 | [2] = { 70, 5000, 145, 1450, }, |
| 289 | [3] = { 60, 4900, 115, 1150, }, |
| 290 | [4] = { 50, 3838, 90, 900, }, |
| 291 | [5] = { 40, 2904, 55, 550, }, |
| 292 | [6] = { 30, 2337, 30, 300, }, |
| 293 | [7] = { 20, 1608, 15, 150, }, |
| 294 | [8] = { 10, 800, 10, 100, }, |
| 295 | [9] = { 0, 0, 0, 50, } |
| 296 | }" |
| 297 | |
| 298 | ## Fan options |
| 299 | register "options.fan.fine_grained_control" = "1" |
| 300 | register "options.fan.step_size" = "2" |
| 301 | |
| 302 | device generic 0 on end |
| 303 | end |
| 304 | end # DPTF |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 305 | device pci 05.0 on end # IPU |
| 306 | device pci 06.0 on end # PEG60 |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 307 | device pci 06.2 on end # PEG62 |
V Sowmya | 73caae9 | 2020-11-06 13:47:04 +0530 | [diff] [blame] | 308 | device pci 07.0 on end # TBT_PCIe0 |
| 309 | device pci 07.1 on end # TBT_PCIe1 |
| 310 | device pci 07.2 on end # TBT_PCIe2 |
| 311 | device pci 07.3 on end # TBT_PCIe3 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 312 | device pci 08.0 off end # GNA |
| 313 | device pci 09.0 off end # NPK |
| 314 | device pci 0a.0 off end # Crash-log SRAM |
| 315 | device pci 0d.0 on end # USB xHCI |
V Sowmya | 73caae9 | 2020-11-06 13:47:04 +0530 | [diff] [blame] | 316 | device pci 0d.1 on end # USB xDCI (OTG) |
| 317 | device pci 0d.2 on end # TBT DMA0 |
| 318 | device pci 0d.3 on end # TBT DMA1 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 319 | device pci 0e.0 off end # VMD |
| 320 | device pci 10.0 off end |
| 321 | device pci 10.1 off end |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 322 | device pci 12.0 off end # SensorHUB |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 323 | device pci 12.6 off end # GSPI2 |
| 324 | device pci 13.0 off end # GSPI3 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 325 | device pci 14.0 on |
| 326 | chip drivers/usb/acpi |
| 327 | register "desc" = ""Root Hub"" |
| 328 | register "type" = "UPC_TYPE_HUB" |
| 329 | device usb 0.0 on |
| 330 | chip drivers/usb/acpi |
| 331 | register "desc" = ""Bluetooth"" |
| 332 | register "type" = "UPC_TYPE_INTERNAL" |
| 333 | device usb 2.9 on end |
| 334 | end |
| 335 | end |
| 336 | end |
| 337 | end # USB3.1 xHCI |
| 338 | device pci 14.1 off end # USB3.1 xDCI |
| 339 | device pci 14.2 off end # Shared RAM |
Furquan Shaikh | edac4ef | 2020-10-09 08:50:14 -0700 | [diff] [blame] | 340 | device pci 14.3 on |
| 341 | chip drivers/wifi/generic |
| 342 | register "wake" = "GPE0_PME_B0" |
| 343 | device generic 0 on end |
| 344 | end |
| 345 | end # CNVi: WiFi |
Meera Ravindranath | 56ccbf3 | 2020-12-01 20:33:39 +0530 | [diff] [blame] | 346 | device pci 15.0 on end # I2C0 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 347 | device pci 15.1 on end # I2C1 |
| 348 | device pci 15.2 on end # I2C2 |
| 349 | device pci 15.3 on end # I2C3 |
| 350 | device pci 16.0 on end # HECI1 |
| 351 | device pci 16.1 off end # HECI2 |
| 352 | device pci 16.2 off end # CSME |
| 353 | device pci 16.3 off end # CSME |
| 354 | device pci 16.4 off end # HECI3 |
| 355 | device pci 16.5 off end # HECI4 |
| 356 | device pci 17.0 on end # SATA |
| 357 | device pci 19.0 off end # I2C4 |
| 358 | device pci 19.1 on end # I2C5 |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 359 | device pci 19.2 off end # UART2 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 360 | device pci 1c.0 on end # RP1 |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 361 | device pci 1c.1 off end # RP2 |
Subrata Banik | 8c4aa15 | 2021-01-09 16:38:34 +0530 | [diff] [blame] | 362 | device pci 1c.2 on end # RP3 # W/A to FSP issue |
| 363 | device pci 1c.3 on end # RP4 # W/A to FSP issue |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 364 | device pci 1c.4 on end # RP5 |
| 365 | device pci 1c.5 on end # RP6 |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 366 | device pci 1c.6 off end # RP7 |
Subrata Banik | 840679d | 2020-11-27 00:46:18 +0530 | [diff] [blame] | 367 | device pci 1c.7 on end # RP8 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 368 | device pci 1d.0 on end # RP9 |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 369 | device pci 1d.1 off end # RP10 |
Subrata Banik | 6147314 | 2020-10-14 22:06:48 +0530 | [diff] [blame] | 370 | device pci 1d.2 on end # RP11 |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 371 | device pci 1d.3 off end # RP12 |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 372 | device pci 1e.0 on end # UART0 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 373 | device pci 1e.1 off end # UART1 |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 374 | device pci 1e.2 on end # GSPI0 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 375 | device pci 1e.3 off end # GSPI1 |
| 376 | device pci 1f.0 on end # eSPI |
| 377 | device pci 1f.1 on end # P2SB |
| 378 | device pci 1f.2 hidden end # PMC |
| 379 | device pci 1f.3 on |
| 380 | chip drivers/intel/soundwire |
| 381 | device generic 0 on |
Sridhar Siricilla | f2de1e7 | 2020-11-05 14:18:38 +0530 | [diff] [blame] | 382 | chip drivers/soundwire/alc711 |
| 383 | # SoundWire Link 0 ID 1 |
| 384 | register "desc" = ""Headset Codec"" |
| 385 | device generic 0.1 on end |
| 386 | end |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 387 | end |
| 388 | end |
| 389 | end # Intel Audio SNDW |
| 390 | device pci 1f.4 on end # SMBus |
| 391 | device pci 1f.5 on end # SPI |
| 392 | device pci 1f.6 off end # GbE |
| 393 | device pci 1f.7 off end # TH |
| 394 | end |
| 395 | end |