Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 1 | chip soc/intel/alderlake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 7 | # GPE configuration |
| 8 | # Note that GPE events called out in ASL code rely on this |
| 9 | # route. i.e. If this route changes then the affected GPE |
| 10 | # offset bits also need to be changed. |
| 11 | register "pmc_gpe0_dw0" = "GPP_B" |
| 12 | register "pmc_gpe0_dw1" = "GPP_D" |
| 13 | register "pmc_gpe0_dw2" = "GPP_E" |
| 14 | |
Sridhar Siricilla | edc6da2 | 2021-04-07 10:18:43 +0530 | [diff] [blame^] | 15 | # Enable HECI1 interface |
| 16 | register "HeciEnabled" = "1" |
| 17 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 18 | # FSP configuration |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 19 | |
Cliff Huang | b1a128f | 2021-02-10 18:07:46 -0800 | [diff] [blame] | 20 | # Enable CNVi BT |
| 21 | register "CnviBtCore" = "true" |
| 22 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 23 | register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 |
| 24 | register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 |
| 25 | register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 |
| 26 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN |
| 27 | register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 |
| 28 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector |
| 29 | register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 |
| 30 | register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 |
| 31 | register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 |
| 32 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN |
| 33 | |
| 34 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 |
| 35 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 |
| 36 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 |
| 37 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN |
| 38 | |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 39 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 40 | register "gen1_dec" = "0x00fc0801" |
| 41 | register "gen2_dec" = "0x000c0201" |
| 42 | # EC memory map range is 0x900-0x9ff |
| 43 | register "gen3_dec" = "0x00fc0901" |
| 44 | register "gen4_dec" = "0x000c0081" |
| 45 | |
Subrata Banik | f965077 | 2021-03-24 16:49:14 +0530 | [diff] [blame] | 46 | # This disabled autonomous GPIO power management, otherwise |
| 47 | # old cr50 FW only supports short pulses; need to clarify |
| 48 | # the minimum PCH IRQ pulse width with Intel, b/180111628 |
| 49 | register "gpio_override_pm" = "1" |
| 50 | register "gpio_pm[COMM_0]" = "0" |
| 51 | register "gpio_pm[COMM_1]" = "0" |
| 52 | register "gpio_pm[COMM_2]" = "0" |
| 53 | register "gpio_pm[COMM_4]" = "0" |
| 54 | register "gpio_pm[COMM_5]" = "0" |
| 55 | |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 56 | register "PrmrrSize" = "0" |
| 57 | |
| 58 | # Enable PCH PCIE RP 5 using CLK 2 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 59 | register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| 60 | .clk_src = 2, |
| 61 | .clk_req = 2, |
| 62 | .flags = PCIE_RP_CLK_REQ_DETECT, |
| 63 | }" |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 64 | |
| 65 | # Enable PCH PCIE RP 6 using CLK 5 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 66 | register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| 67 | .clk_src = 5, |
| 68 | .clk_req = 5, |
| 69 | .flags = PCIE_RP_CLK_REQ_DETECT, |
| 70 | }" |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 71 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 72 | # Enable PCH PCIE RP 8 using free running CLK (0x80) |
| 73 | # Clock source is shared with LAN and hence marked as free running. |
| 74 | register "pch_pcie_rp[PCH_RP(8)]" = "{ |
| 75 | .flags = PCIE_RP_CLK_SRC_UNUSED, |
| 76 | }" |
| 77 | register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" |
Subrata Banik | 840679d | 2020-11-27 00:46:18 +0530 | [diff] [blame] | 78 | |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 79 | # Enable PCH PCIE RP 9 using CLK 1 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 80 | register "pch_pcie_rp[PCH_RP(9)]" = "{ |
| 81 | .clk_src = 1, |
| 82 | .clk_req = 1, |
| 83 | .flags = PCIE_RP_CLK_REQ_DETECT, |
| 84 | }" |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 85 | |
Subrata Banik | 6147314 | 2020-10-14 22:06:48 +0530 | [diff] [blame] | 86 | # Enable PCH PCIE RP 11 for optane |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 87 | register "pch_pcie_rp[PCH_RP(11)]" = "{ |
| 88 | .flags = PCIE_RP_CLK_SRC_UNUSED, |
| 89 | }" |
| 90 | |
Subrata Banik | 3f561a8 | 2020-10-14 22:12:12 +0530 | [diff] [blame] | 91 | # Hybrid storage mode |
| 92 | register "HybridStorageMode" = "1" |
Subrata Banik | 6147314 | 2020-10-14 22:06:48 +0530 | [diff] [blame] | 93 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 94 | # Enable CPU PCIE RP 1 using CLK 0 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 95 | register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| 96 | .clk_req = 0, |
| 97 | .clk_src = 0, |
| 98 | }" |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 99 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 100 | # Enable CPU PCIE RP 2 using CLK 3 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 101 | register "cpu_pcie_rp[CPU_RP(2)]" = "{ |
| 102 | .clk_req = 3, |
| 103 | .clk_src = 3, |
| 104 | }" |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 105 | |
| 106 | # Enable CPU PCIE RP 3 using CLK 4 |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 107 | register "cpu_pcie_rp[CPU_RP(3)]" = "{ |
| 108 | .clk_req = 4, |
| 109 | .clk_src = 4, |
| 110 | }" |
Subrata Banik | 8c4aa15 | 2021-01-09 16:38:34 +0530 | [diff] [blame] | 111 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 112 | register "SataSalpSupport" = "1" |
| 113 | |
| 114 | register "SataPortsEnable" = "{ |
Subrata Banik | 1d18c8e | 2021-01-29 19:05:30 +0530 | [diff] [blame] | 115 | [0] = 1, |
| 116 | [1] = 1, |
| 117 | [2] = 1, |
| 118 | [3] = 1, |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 119 | }" |
| 120 | |
| 121 | register "SataPortsDevSlp" = "{ |
Subrata Banik | 1d18c8e | 2021-01-29 19:05:30 +0530 | [diff] [blame] | 122 | [0] = 1, |
| 123 | [1] = 1, |
| 124 | [2] = 1, |
| 125 | [3] = 1, |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 126 | }" |
| 127 | |
| 128 | # Enable EDP in PortA |
| 129 | register "DdiPortAConfig" = "1" |
Subrata Banik | 8ed53ec | 2020-11-21 19:50:56 +0530 | [diff] [blame] | 130 | # Enable HDMI in Port B |
| 131 | register "DdiPortBDdc" = "1" |
| 132 | register "DdiPortBHpd" = "1" |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 133 | |
| 134 | # TCSS USB3 |
| 135 | register "TcssAuxOri" = "0" |
| 136 | |
| 137 | register "s0ix_enable" = "1" |
| 138 | |
| 139 | register "SerialIoI2cMode" = "{ |
Subrata Banik | 1d18c8e | 2021-01-29 19:05:30 +0530 | [diff] [blame] | 140 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 141 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 142 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 143 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 144 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 145 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 146 | }" |
| 147 | |
| 148 | register "SerialIoGSpiMode" = "{ |
| 149 | [PchSerialIoIndexGSPI0] = PchSerialIoPci, |
| 150 | [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| 151 | [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, |
| 152 | [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, |
| 153 | }" |
| 154 | |
| 155 | register "SerialIoGSpiCsMode" = "{ |
| 156 | [PchSerialIoIndexGSPI0] = 0, |
| 157 | [PchSerialIoIndexGSPI1] = 0, |
| 158 | [PchSerialIoIndexGSPI2] = 0, |
| 159 | [PchSerialIoIndexGSPI3] = 0, |
| 160 | }" |
| 161 | |
| 162 | register "SerialIoGSpiCsState" = "{ |
| 163 | [PchSerialIoIndexGSPI0] = 0, |
| 164 | [PchSerialIoIndexGSPI1] = 0, |
| 165 | [PchSerialIoIndexGSPI2] = 0, |
| 166 | [PchSerialIoIndexGSPI3] = 0, |
| 167 | }" |
| 168 | |
| 169 | register "SerialIoUartMode" = "{ |
| 170 | [PchSerialIoIndexUART0] = PchSerialIoSkipInit, |
| 171 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 172 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 173 | }" |
| 174 | |
| 175 | # HD Audio |
| 176 | register "PchHdaDspEnable" = "1" |
| 177 | register "PchHdaAudioLinkHdaEnable" = "0" |
| 178 | register "PchHdaAudioLinkDmicEnable[0]" = "1" |
| 179 | register "PchHdaAudioLinkDmicEnable[1]" = "1" |
| 180 | register "PchHdaAudioLinkSndwEnable[0]" = "1" |
| 181 | register "PchHdaAudioLinkSndwEnable[1]" = "1" |
| 182 | # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| 183 | register "PchHdaIDispLinkTmode" = "2" |
| 184 | # iDisp-Link Freq 4: 96MHz, 3: 48MHz. |
| 185 | register "PchHdaIDispLinkFrequency" = "4" |
| 186 | # Not disconnected/enumerable |
| 187 | register "PchHdaIDispCodecDisconnect" = "0" |
| 188 | |
Usha P | f02fa4a | 2021-02-23 17:56:46 +0530 | [diff] [blame] | 189 | register "CnviBtAudioOffload" = "true" |
| 190 | |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 191 | # Intel Common SoC Config |
| 192 | register "common_soc_config" = "{ |
| 193 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 194 | .i2c[0] = { |
| 195 | .speed = I2C_SPEED_FAST, |
| 196 | }, |
| 197 | .i2c[1] = { |
| 198 | .speed = I2C_SPEED_FAST, |
| 199 | }, |
| 200 | .i2c[2] = { |
| 201 | .speed = I2C_SPEED_FAST, |
| 202 | }, |
| 203 | .i2c[3] = { |
| 204 | .speed = I2C_SPEED_FAST, |
| 205 | }, |
| 206 | .i2c[5] = { |
| 207 | .speed = I2C_SPEED_FAST, |
| 208 | }, |
| 209 | }" |
| 210 | |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 211 | device domain 0 on |
| 212 | device pci 00.0 on end # Host Bridge |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 213 | device pci 01.0 on end # PEG10 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 214 | device pci 02.0 on end # Graphics |
| 215 | device pci 04.0 on end # DPTF |
| 216 | device pci 05.0 on end # IPU |
| 217 | device pci 06.0 on end # PEG60 |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 218 | device pci 06.2 on end # PEG62 |
V Sowmya | 73caae9 | 2020-11-06 13:47:04 +0530 | [diff] [blame] | 219 | device pci 07.0 on end # TBT_PCIe0 |
| 220 | device pci 07.1 on end # TBT_PCIe1 |
| 221 | device pci 07.2 on end # TBT_PCIe2 |
| 222 | device pci 07.3 on end # TBT_PCIe3 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 223 | device pci 08.0 off end # GNA |
| 224 | device pci 09.0 off end # NPK |
| 225 | device pci 0a.0 off end # Crash-log SRAM |
| 226 | device pci 0d.0 on end # USB xHCI |
V Sowmya | 73caae9 | 2020-11-06 13:47:04 +0530 | [diff] [blame] | 227 | device pci 0d.1 on end # USB xDCI (OTG) |
| 228 | device pci 0d.2 on end # TBT DMA0 |
| 229 | device pci 0d.3 on end # TBT DMA1 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 230 | device pci 0e.0 off end # VMD |
| 231 | device pci 10.0 off end |
| 232 | device pci 10.1 off end |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 233 | device pci 10.6 off end # THC0 |
| 234 | device pci 10.7 off end # THC1 |
| 235 | device pci 11.0 off end |
| 236 | device pci 11.1 off end |
| 237 | device pci 11.2 off end |
| 238 | device pci 11.3 off end |
| 239 | device pci 11.4 off end |
| 240 | device pci 11.5 off end |
| 241 | device pci 12.0 off end # SensorHUB |
| 242 | device pci 12.5 off end |
| 243 | device pci 12.6 off end # GSPI2 |
| 244 | device pci 13.0 off end # GSPI3 |
| 245 | device pci 13.1 off end |
| 246 | device pci 14.0 on |
| 247 | chip drivers/usb/acpi |
| 248 | register "desc" = ""Root Hub"" |
| 249 | register "type" = "UPC_TYPE_HUB" |
| 250 | device usb 0.0 on |
| 251 | chip drivers/usb/acpi |
| 252 | register "desc" = ""Bluetooth"" |
| 253 | register "type" = "UPC_TYPE_INTERNAL" |
| 254 | device usb 2.9 on end |
| 255 | end |
| 256 | end |
| 257 | end |
| 258 | end # USB3.1 xHCI |
| 259 | device pci 14.1 off end # USB3.1 xDCI |
| 260 | device pci 14.2 off end # Shared RAM |
Furquan Shaikh | edac4ef | 2020-10-09 08:50:14 -0700 | [diff] [blame] | 261 | device pci 14.3 on |
| 262 | chip drivers/wifi/generic |
| 263 | register "wake" = "GPE0_PME_B0" |
| 264 | device generic 0 on end |
| 265 | end |
| 266 | end # CNVi: WiFi |
Meera Ravindranath | 56ccbf3 | 2020-12-01 20:33:39 +0530 | [diff] [blame] | 267 | device pci 15.0 on end # I2C0 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 268 | device pci 15.1 on end # I2C1 |
| 269 | device pci 15.2 on end # I2C2 |
| 270 | device pci 15.3 on end # I2C3 |
| 271 | device pci 16.0 on end # HECI1 |
| 272 | device pci 16.1 off end # HECI2 |
| 273 | device pci 16.2 off end # CSME |
| 274 | device pci 16.3 off end # CSME |
| 275 | device pci 16.4 off end # HECI3 |
| 276 | device pci 16.5 off end # HECI4 |
| 277 | device pci 17.0 on end # SATA |
| 278 | device pci 19.0 off end # I2C4 |
| 279 | device pci 19.1 on end # I2C5 |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 280 | device pci 19.2 off end # UART2 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 281 | device pci 1c.0 on end # RP1 |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 282 | device pci 1c.1 off end # RP2 |
Subrata Banik | 8c4aa15 | 2021-01-09 16:38:34 +0530 | [diff] [blame] | 283 | device pci 1c.2 on end # RP3 # W/A to FSP issue |
| 284 | device pci 1c.3 on end # RP4 # W/A to FSP issue |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 285 | device pci 1c.4 on end # RP5 |
| 286 | device pci 1c.5 on end # RP6 |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 287 | device pci 1c.6 off end # RP7 |
Subrata Banik | 840679d | 2020-11-27 00:46:18 +0530 | [diff] [blame] | 288 | device pci 1c.7 on end # RP8 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 289 | device pci 1d.0 on end # RP9 |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 290 | device pci 1d.1 off end # RP10 |
Subrata Banik | 6147314 | 2020-10-14 22:06:48 +0530 | [diff] [blame] | 291 | device pci 1d.2 on end # RP11 |
Subrata Banik | 16e4106 | 2020-10-06 20:13:06 +0530 | [diff] [blame] | 292 | device pci 1d.3 off end # RP12 |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 293 | device pci 1e.0 on end # UART0 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 294 | device pci 1e.1 off end # UART1 |
Subrata Banik | 9b4f221 | 2020-10-10 15:53:33 +0530 | [diff] [blame] | 295 | device pci 1e.2 on end # GSPI0 |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 296 | device pci 1e.3 off end # GSPI1 |
| 297 | device pci 1f.0 on end # eSPI |
| 298 | device pci 1f.1 on end # P2SB |
| 299 | device pci 1f.2 hidden end # PMC |
| 300 | device pci 1f.3 on |
| 301 | chip drivers/intel/soundwire |
| 302 | device generic 0 on |
Sridhar Siricilla | f2de1e7 | 2020-11-05 14:18:38 +0530 | [diff] [blame] | 303 | chip drivers/soundwire/alc711 |
| 304 | # SoundWire Link 0 ID 1 |
| 305 | register "desc" = ""Headset Codec"" |
| 306 | device generic 0.1 on end |
| 307 | end |
Subrata Banik | efc4009 | 2020-10-05 21:04:22 +0530 | [diff] [blame] | 308 | end |
| 309 | end |
| 310 | end # Intel Audio SNDW |
| 311 | device pci 1f.4 on end # SMBus |
| 312 | device pci 1f.5 on end # SPI |
| 313 | device pci 1f.6 off end # GbE |
| 314 | device pci 1f.7 off end # TH |
| 315 | end |
| 316 | end |