Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: Apache-2.0 */ |
| 2 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 3 | /* See the file LICENSE for further information */ |
| 4 | |
| 5 | #ifndef _SIFIVE_UX00DDR_H |
| 6 | #define _SIFIVE_UX00DDR_H |
| 7 | |
| 8 | #ifndef __ASSEMBLER__ |
| 9 | |
| 10 | #include <stdint.h> |
| 11 | #include <stddef.h> |
| 12 | |
| 13 | #define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) |
| 14 | |
| 15 | #define DRAM_CLASS_OFFSET 8 |
| 16 | #define DRAM_CLASS_DDR4 0xA |
| 17 | #define OPTIMAL_RMODW_EN_OFFSET 0 |
| 18 | #define DISABLE_RD_INTERLEAVE_OFFSET 16 |
| 19 | #define OUT_OF_RANGE_OFFSET 1 |
| 20 | #define MULTIPLE_OUT_OF_RANGE_OFFSET 2 |
| 21 | #define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7 |
| 22 | #define MC_INIT_COMPLETE_OFFSET 8 |
| 23 | #define LEVELING_OPERATION_COMPLETED_OFFSET 22 |
| 24 | #define DFI_PHY_WRLELV_MODE_OFFSET 24 |
| 25 | #define DFI_PHY_RDLVL_MODE_OFFSET 24 |
| 26 | #define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0 |
| 27 | #define VREF_EN_OFFSET 24 |
| 28 | #define PORT_ADDR_PROTECTION_EN_OFFSET 0 |
| 29 | #define AXI0_ADDRESS_RANGE_ENABLE 8 |
| 30 | #define AXI0_RANGE_PROT_BITS_0_OFFSET 24 |
| 31 | #define RDLVL_EN_OFFSET 16 |
| 32 | #define RDLVL_GATE_EN_OFFSET 24 |
| 33 | #define WRLVL_EN_OFFSET 0 |
| 34 | |
| 35 | #define PHY_RX_CAL_DQ0_0_OFFSET 0 |
| 36 | #define PHY_RX_CAL_DQ1_0_OFFSET 16 |
| 37 | |
| 38 | static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings) { |
| 39 | unsigned int i; |
| 40 | for (i=1152;i<=1214;i++) { |
| 41 | uint32_t physet = physettings[i]; |
| 42 | /*if (physet!=0)*/ ddrphyreg[i] = physet; |
| 43 | } |
| 44 | for (i=0;i<=1151;i++) { |
| 45 | uint32_t physet = physettings[i]; |
| 46 | /*if (physet!=0)*/ ddrphyreg[i] = physet; |
| 47 | } |
| 48 | } |
| 49 | |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 50 | static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) { |
Elyes Haouas | e53baa6 | 2023-09-09 08:50:01 +0200 | [diff] [blame] | 51 | volatile uint32_t *ddrctlreg = (volatile uint32_t *)ahbregaddr; |
| 52 | volatile uint32_t *ddrphyreg = ((volatile uint32_t *)ahbregaddr) + (0x2000 / sizeof(uint32_t)); |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 53 | |
| 54 | unsigned int i; |
| 55 | for (i=0;i<=264;i++) { |
| 56 | uint32_t ctlset = ctlsettings[i]; |
| 57 | /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset; |
| 58 | } |
| 59 | |
| 60 | phy_reset(ddrphyreg, physettings); |
| 61 | } |
| 62 | |
| 63 | static inline void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend) { |
| 64 | // START register at ddrctl register base offset 0 |
| 65 | uint32_t regdata = _REG32(0<<2, ahbregaddr); |
| 66 | regdata |= 0x1; |
| 67 | _REG32(0<<2, ahbregaddr) = regdata; |
| 68 | // WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210 |
| 69 | while ((_REG32(132<<2, ahbregaddr) & (1<<MC_INIT_COMPLETE_OFFSET)) == 0) {} |
| 70 | |
| 71 | // Disable the BusBlocker in front of the controller AXI slave ports |
| 72 | volatile uint64_t *filterreg = (volatile uint64_t *)filteraddr; |
| 73 | filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2); |
| 74 | // ^^ RWX + TOR |
| 75 | } |
| 76 | |
| 77 | static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) { |
| 78 | // Mask off Bit 8 of Interrupt Status |
| 79 | // Bit [8] The MC initialization has been completed |
| 80 | _REG32(136<<2, ahbregaddr) |= (1<<MC_INIT_COMPLETE_OFFSET); |
| 81 | } |
| 82 | |
| 83 | static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) { |
| 84 | // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 85 | // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occurred |
| 86 | // Bit [1] A memory access outside the defined PHYSICAL memory space has occurred |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 87 | _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET)); |
| 88 | } |
| 89 | |
| 90 | static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) { |
| 91 | // Mask off Bit 7 of Interrupt Status |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 92 | // Bit [7] An error occurred on the port command channel |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 93 | _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET); |
| 94 | } |
| 95 | |
| 96 | static inline void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr) { |
| 97 | // Mask off Bit 22 of Interrupt Status |
| 98 | // Bit [22] The leveling operation has completed |
| 99 | _REG32(136<<2, ahbregaddr) |= (1<<LEVELING_OPERATION_COMPLETED_OFFSET); |
| 100 | } |
| 101 | |
| 102 | static inline void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr) { |
| 103 | _REG32(209<<2, ahbregaddr) = 0x0; |
| 104 | size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1; |
Elyes Haouas | e53baa6 | 2023-09-09 08:50:01 +0200 | [diff] [blame] | 105 | _REG32(210<<2, ahbregaddr) = ((uint32_t)end_addr_16Kblocks); |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 106 | _REG32(212<<2, ahbregaddr) = 0x0; |
| 107 | _REG32(214<<2, ahbregaddr) = 0x0; |
| 108 | _REG32(216<<2, ahbregaddr) = 0x0; |
| 109 | _REG32(224<<2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET); |
| 110 | _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF; |
| 111 | _REG32(208<<2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE); |
| 112 | _REG32(208<<2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET); |
| 113 | |
| 114 | } |
| 115 | |
| 116 | static inline void ux00ddr_disableaxireadinterleave(size_t ahbregaddr) { |
| 117 | _REG32(120<<2, ahbregaddr) |= (1<<DISABLE_RD_INTERLEAVE_OFFSET); |
| 118 | } |
| 119 | |
| 120 | static inline void ux00ddr_disableoptimalrmodw(size_t ahbregaddr) { |
| 121 | _REG32(21<<2, ahbregaddr) &= (~(1<<OPTIMAL_RMODW_EN_OFFSET)); |
| 122 | } |
| 123 | |
| 124 | static inline void ux00ddr_enablewriteleveling(size_t ahbregaddr) { |
| 125 | _REG32(170<<2, ahbregaddr) |= ((1<<WRLVL_EN_OFFSET) | (1<<DFI_PHY_WRLELV_MODE_OFFSET)); |
| 126 | } |
| 127 | |
| 128 | static inline void ux00ddr_enablereadleveling(size_t ahbregaddr) { |
| 129 | _REG32(181<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_MODE_OFFSET); |
| 130 | _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_EN_OFFSET); |
| 131 | } |
| 132 | |
| 133 | static inline void ux00ddr_enablereadlevelinggate(size_t ahbregaddr) { |
| 134 | _REG32(260<<2, ahbregaddr) |= (1<<RDLVL_GATE_EN_OFFSET); |
| 135 | _REG32(182<<2, ahbregaddr) |= (1<<DFI_PHY_RDLVL_GATE_MODE_OFFSET); |
| 136 | } |
| 137 | |
| 138 | static inline void ux00ddr_enablevreftraining(size_t ahbregaddr) { |
| 139 | _REG32(184<<2, ahbregaddr) |= (1<<VREF_EN_OFFSET); |
| 140 | } |
| 141 | |
| 142 | static inline uint32_t ux00ddr_getdramclass(size_t ahbregaddr) { |
| 143 | return ((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF); |
| 144 | } |
| 145 | |
| 146 | static inline uint64_t ux00ddr_phy_fixup(size_t ahbregaddr) { |
| 147 | // return bitmask of failed lanes |
| 148 | |
| 149 | size_t ddrphyreg = ahbregaddr + 0x2000; |
| 150 | |
Arthur Heymans | 81decdf | 2023-05-19 12:20:15 +0200 | [diff] [blame] | 151 | // uint64_t fails=0; |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 152 | uint32_t slicebase = 0; |
Arthur Heymans | 81decdf | 2023-05-19 12:20:15 +0200 | [diff] [blame] | 153 | // uint32_t dq = 0; |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 154 | |
| 155 | // check errata condition |
| 156 | for (uint32_t slice = 0; slice < 8; slice++) { |
| 157 | uint32_t regbase = slicebase + 34; |
| 158 | for (uint32_t reg = 0 ; reg < 4; reg++) { |
| 159 | uint32_t updownreg = _REG32((regbase+reg)<<2, ddrphyreg); |
| 160 | for (uint32_t bit = 0; bit < 2; bit++) { |
| 161 | uint32_t phy_rx_cal_dqn_0_offset; |
| 162 | |
| 163 | if (bit==0) { |
| 164 | phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET; |
| 165 | }else{ |
| 166 | phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET; |
| 167 | } |
| 168 | |
| 169 | uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F; |
| 170 | uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F; |
| 171 | |
| 172 | uint8_t failc0 = ((down == 0) && (up == 0x3F)); |
| 173 | uint8_t failc1 = ((up == 0) && (down == 0x3F)); |
| 174 | |
| 175 | // print error message on failure |
| 176 | if (failc0 || failc1) { |
| 177 | //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n"); |
Arthur Heymans | 81decdf | 2023-05-19 12:20:15 +0200 | [diff] [blame] | 178 | //fails |= (1<<dq); |
Arthur Heymans | 1b2c03b | 2022-03-24 01:23:31 +0100 | [diff] [blame] | 179 | /* char slicelsc = '0'; */ |
| 180 | /* char slicemsc = '0'; */ |
| 181 | /* slicelsc += (dq % 10); */ |
| 182 | /* slicemsc += (dq / 10); */ |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 183 | //uart_puts((void*) UART0_CTRL_ADDR, "S "); |
| 184 | //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc); |
| 185 | //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc); |
| 186 | //if (failc0) uart_puts((void*) UART0_CTRL_ADDR, "U"); |
| 187 | //else uart_puts((void*) UART0_CTRL_ADDR, "D"); |
| 188 | //uart_puts((void*) UART0_CTRL_ADDR, "\n"); |
| 189 | } |
Arthur Heymans | 81decdf | 2023-05-19 12:20:15 +0200 | [diff] [blame] | 190 | //dq++; |
Philipp Hug | 9159572 | 2018-09-13 22:18:06 +0200 | [diff] [blame] | 191 | } |
| 192 | } |
| 193 | slicebase+=128; |
| 194 | } |
| 195 | return (0); |
| 196 | } |
| 197 | |
| 198 | #endif |
| 199 | |
| 200 | #endif |