blob: f0e9d44bbbceea2342847f84b2736254fec73df1 [file] [log] [blame]
Angel Ponsfabfe9d2020-04-05 15:47:07 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Aamir Bohradd7acaa2020-03-25 11:36:22 +05302
Chia-Ling Houb5a03282023-06-07 16:53:00 +08003#include <chip.h>
4#include <console/console.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +05305#include <device/device.h>
Sumeet R Pawnikard8b4ea92020-05-26 19:59:45 +05306#include <delay.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +05307#include <device/pci.h>
8#include <device/pci_ops.h>
9#include <intelblocks/systemagent.h>
Sumeet R Pawnikard8b4ea92020-05-26 19:59:45 +053010#include <intelblocks/power_limit.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +053011#include <soc/iomap.h>
Sumeet R Pawnikard8b4ea92020-05-26 19:59:45 +053012#include <soc/soc_chip.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +053013#include <soc/systemagent.h>
14
15/*
16 * SoC implementation
17 *
18 * Add all known fixed memory ranges for Host Controller/Memory
19 * controller.
20 */
21void soc_add_fixed_mmio_resources(struct device *dev, int *index)
22{
23 static const struct sa_mmio_descriptor soc_fixed_resources[] = {
Shelley Chen4e9bb332021-10-20 15:43:45 -070024 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
Aamir Bohradd7acaa2020-03-25 11:36:22 +053025 "PCIEXBAR" },
26 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
27 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
28 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
29 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
30 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
Aamir Bohradd7acaa2020-03-25 11:36:22 +053031 };
32
33 sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
34 ARRAY_SIZE(soc_fixed_resources));
35
36 /* Add Vt-d resources if VT-d is enabled */
37 if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
38 return;
39
40 sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
41 ARRAY_SIZE(soc_vtd_resources));
42}
43
44/*
45 * SoC implementation
46 *
47 * Perform System Agent Initialization during Ramstage phase.
48 */
49void soc_systemagent_init(struct device *dev)
50{
Sumeet R Pawnikard8b4ea92020-05-26 19:59:45 +053051 struct soc_power_limits_config *soc_config;
52 config_t *config;
Chia-Ling Houb5a03282023-06-07 16:53:00 +080053 uint16_t sa_pci_id;
54 uint8_t tdp;
55 size_t i = 0;
Sumeet R Pawnikard8b4ea92020-05-26 19:59:45 +053056
Aamir Bohradd7acaa2020-03-25 11:36:22 +053057 /* Enable Power Aware Interrupt Routing */
58 enable_power_aware_intr();
59
60 /* Enable BIOS Reset CPL */
61 enable_bios_reset_cpl();
Sumeet R Pawnikard8b4ea92020-05-26 19:59:45 +053062
63 mdelay(1);
64 config = config_of_soc();
Chia-Ling Houb5a03282023-06-07 16:53:00 +080065
66 /* Get System Agent PCI ID */
67 sa_pci_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xFFFF;
68
69 if (sa_pci_id != 0xFFFF) {
70 tdp = get_cpu_tdp();
71
72 /* Choose power limits configuration based on the CPU SA PCI ID and
73 * CPU TDP value. */
74 for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) {
75 if (sa_pci_id == cpuid_to_jsl[i].pci_did &&
76 tdp == cpuid_to_jsl[i].cpu_tdp) {
77 soc_config = &config->power_limits_config[cpuid_to_jsl[i].limits];
78 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
79 break;
80 }
81 }
82 }
83
84 if (i == ARRAY_SIZE(cpuid_to_jsl) || sa_pci_id == 0xFFFF) {
85 printk(BIOS_ERR, "unknown SA ID: 0x%4x, can't find its TDP."
86 " Skipped power limits configuration.\n",
87 sa_pci_id);
88 return;
89 }
Aamir Bohradd7acaa2020-03-25 11:36:22 +053090}