| Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | /* |
| 16 | * This file is created based on Intel Tiger Lake Processor SA Datasheet |
| 17 | * Document number: 571131 |
| 18 | * Chapter number: 3 |
| 19 | */ |
| 20 | |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include <intelblocks/systemagent.h> |
| 25 | #include <soc/iomap.h> |
| 26 | #include <soc/systemagent.h> |
| 27 | |
| 28 | /* |
| 29 | * SoC implementation |
| 30 | * |
| 31 | * Add all known fixed memory ranges for Host Controller/Memory |
| 32 | * controller. |
| 33 | */ |
| 34 | void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
| 35 | { |
| 36 | static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
| 37 | { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, |
| 38 | "PCIEXBAR" }, |
| 39 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 40 | { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, |
| 41 | { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, |
| 42 | { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, |
| 43 | { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, |
| 44 | /* |
| 45 | * PMC pci device gets hidden from PCI bus due to Silicon |
| 46 | * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with |
| 47 | * SA resources to ensure that PMCBAR falls under PCI reserved |
| 48 | * memory range. |
| 49 | * |
| 50 | * Note: Don't add any more resource with same offset 0x10 |
| 51 | * under this device space. |
| 52 | */ |
| 53 | { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, |
| 54 | "PMCBAR" }, |
| 55 | }; |
| 56 | |
| 57 | sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| 58 | ARRAY_SIZE(soc_fixed_resources)); |
| 59 | |
| 60 | /* Add Vt-d resources if VT-d is enabled */ |
| 61 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) |
| 62 | return; |
| 63 | |
| 64 | sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, |
| 65 | ARRAY_SIZE(soc_vtd_resources)); |
| 66 | } |
| 67 | |
| 68 | /* |
| 69 | * SoC implementation |
| 70 | * |
| 71 | * Perform System Agent Initialization during Ramstage phase. |
| 72 | */ |
| 73 | void soc_systemagent_init(struct device *dev) |
| 74 | { |
| 75 | /* Enable Power Aware Interrupt Routing */ |
| 76 | enable_power_aware_intr(); |
| 77 | |
| 78 | /* Enable BIOS Reset CPL */ |
| 79 | enable_bios_reset_cpl(); |
| 80 | } |