Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | |
Dinesh Gehlot | 4da8830 | 2023-01-17 05:46:33 +0000 | [diff] [blame] | 3 | #include <gpio.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 4 | #include <intelblocks/pcr.h> |
| 5 | #include <soc/pcr_ids.h> |
| 6 | #include <soc/pmc.h> |
| 7 | |
| 8 | static const struct reset_mapping rst_map[] = { |
| 9 | { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, |
| 10 | { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, |
| 11 | { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, |
| 12 | }; |
| 13 | |
| 14 | static const struct reset_mapping rst_map_com0[] = { |
| 15 | { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, |
| 16 | { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, |
| 17 | { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, |
| 18 | { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, |
| 19 | }; |
| 20 | |
| 21 | /* |
| 22 | * The GPIO driver for Jasperlake on Windows/Linux expects 32 GPIOs per pad |
| 23 | * group, regardless of whether or not there is a physical pad for each |
| 24 | * exposed GPIO number. |
| 25 | * |
| 26 | * This results in the OS having a sparse GPIO map, and devices that need |
| 27 | * to export an ACPI GPIO must use the OS expected number. |
| 28 | * |
| 29 | * Not all pins are usable as GPIO and those groups do not have a pad base. |
| 30 | * |
| 31 | * This layout matches the Linux kernel pinctrl map for JSP at: |
| 32 | * linux/drivers/pinctrl/intel/pinctrl-jasperlake.c |
| 33 | */ |
| 34 | static const struct pad_group jsl_community0_groups[] = { |
| 35 | |
Maulik V Vaghela | 4a08736 | 2020-10-27 17:19:20 +0530 | [diff] [blame] | 36 | INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 320), /* GPP_F */ |
| 37 | INTEL_GPP(GPP_F0, GPIO_SPI0_IO_2, GPIO_SPI0_CLK_LOOPBK),/* SPI0 */ |
| 38 | INTEL_GPP_BASE(GPP_F0, GPP_B0, GPIO_GSPI1_CLK_LOOPBK, 32),/* GPP_B */ |
| 39 | INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_ESPI_CLK_LOOPBK, 64),/* GPP_A */ |
| 40 | INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ |
| 41 | INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 42 | }; |
| 43 | |
| 44 | static const struct pad_group jsl_community1_groups[] = { |
| 45 | INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */ |
Maulik V Vaghela | 4a08736 | 2020-10-27 17:19:20 +0530 | [diff] [blame] | 46 | INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_SPI1_CLK_LOOPBK, 192),/* GPP_D */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 47 | INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ |
| 48 | INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */ |
| 49 | }; |
| 50 | |
| 51 | /* This community is not visible to the OS */ |
| 52 | static const struct pad_group jsl_community2_groups[] = { |
Maulik V Vaghela | 4a08736 | 2020-10-27 17:19:20 +0530 | [diff] [blame] | 53 | INTEL_GPP(GPD0, GPD0, GPIO_DRAM_RESETB), /* GPD */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 54 | }; |
| 55 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 56 | static const struct pad_group jsl_community4_groups[] = { |
Maulik V Vaghela | 4a08736 | 2020-10-27 17:19:20 +0530 | [diff] [blame] | 57 | INTEL_GPP(GPIO_L_BKLTEN, GPIO_L_BKLTEN, GPIO_MLK_RSTB), /* Reserved */ |
| 58 | INTEL_GPP_BASE(GPIO_L_BKLTEN, GPP_E0, GPP_E23, 288), /* GPP_E */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 59 | }; |
| 60 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 61 | static const struct pad_group jsl_community5_groups[] = { |
Maulik V Vaghela | 4a08736 | 2020-10-27 17:19:20 +0530 | [diff] [blame] | 62 | INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0), /* GPP_G */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { |
| 66 | /* GPP F, B, A, S, R */ |
| 67 | [COMM_0] = { |
| 68 | .port = PID_GPIOCOM0, |
Maulik V Vaghela | e3f030e | 2020-11-05 13:04:38 +0530 | [diff] [blame] | 69 | .first_pad = GPIO_COM0_START, |
| 70 | .last_pad = GPIO_COM0_END, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 71 | .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, |
| 72 | .pad_cfg_base = PAD_CFG_BASE, |
Aseda Aboagye | 4291c82 | 2021-06-17 12:23:40 -0700 | [diff] [blame] | 73 | .pad_cfg_lock_offset = PAD_CFG_LOCK, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 74 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 75 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 76 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
Jonathon Hall | 397c150 | 2023-07-21 13:33:59 -0400 | [diff] [blame] | 77 | .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, |
| 78 | .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 79 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 80 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
Michael Niewöhner | 85610d8 | 2020-11-23 22:02:20 +0100 | [diff] [blame] | 81 | .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, |
| 82 | .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 83 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 84 | .name = "GPP_FBASR", |
| 85 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 86 | .reset_map = rst_map_com0, |
| 87 | .num_reset_vals = ARRAY_SIZE(rst_map_com0), |
| 88 | .groups = jsl_community0_groups, |
| 89 | .num_groups = ARRAY_SIZE(jsl_community0_groups), |
| 90 | }, |
| 91 | /* GPP H, D, VGPIO, C */ |
| 92 | [COMM_1] = { |
| 93 | .port = PID_GPIOCOM1, |
Maulik V Vaghela | e3f030e | 2020-11-05 13:04:38 +0530 | [diff] [blame] | 94 | .first_pad = GPIO_COM1_START, |
| 95 | .last_pad = GPIO_COM1_END, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 96 | .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, |
| 97 | .pad_cfg_base = PAD_CFG_BASE, |
| 98 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 99 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 100 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
Jonathon Hall | 397c150 | 2023-07-21 13:33:59 -0400 | [diff] [blame] | 101 | .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, |
| 102 | .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 103 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 104 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
Michael Niewöhner | 85610d8 | 2020-11-23 22:02:20 +0100 | [diff] [blame] | 105 | .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, |
| 106 | .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 107 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 108 | .name = "GPP_HDC", |
| 109 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 110 | .reset_map = rst_map, |
| 111 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 112 | .groups = jsl_community1_groups, |
| 113 | .num_groups = ARRAY_SIZE(jsl_community1_groups), |
| 114 | }, |
| 115 | /* GPD */ |
| 116 | [COMM_2] = { |
| 117 | .port = PID_GPIOCOM2, |
Maulik V Vaghela | e3f030e | 2020-11-05 13:04:38 +0530 | [diff] [blame] | 118 | .first_pad = GPIO_COM2_START, |
| 119 | .last_pad = GPIO_COM2_END, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 120 | .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, |
| 121 | .pad_cfg_base = PAD_CFG_BASE, |
| 122 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 123 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 124 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
Jonathon Hall | 397c150 | 2023-07-21 13:33:59 -0400 | [diff] [blame] | 125 | .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, |
| 126 | .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 127 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 128 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
| 129 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 130 | .name = "GPD", |
| 131 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 132 | .reset_map = rst_map, |
| 133 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 134 | .groups = jsl_community2_groups, |
| 135 | .num_groups = ARRAY_SIZE(jsl_community2_groups), |
| 136 | }, |
| 137 | /* GPP E */ |
| 138 | [COMM_4] = { |
| 139 | .port = PID_GPIOCOM4, |
Maulik V Vaghela | e3f030e | 2020-11-05 13:04:38 +0530 | [diff] [blame] | 140 | .first_pad = GPIO_COM4_START, |
| 141 | .last_pad = GPIO_COM4_END, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 142 | .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, |
| 143 | .pad_cfg_base = PAD_CFG_BASE, |
| 144 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 145 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 146 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
Jonathon Hall | 397c150 | 2023-07-21 13:33:59 -0400 | [diff] [blame] | 147 | .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, |
| 148 | .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 149 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 150 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
Michael Niewöhner | 85610d8 | 2020-11-23 22:02:20 +0100 | [diff] [blame] | 151 | .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, |
| 152 | .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 153 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 154 | .name = "GPP_E", |
| 155 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 156 | .reset_map = rst_map, |
| 157 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 158 | .groups = jsl_community4_groups, |
| 159 | .num_groups = ARRAY_SIZE(jsl_community4_groups), |
| 160 | }, |
| 161 | /* GPP G */ |
| 162 | [COMM_5] = { |
| 163 | .port = PID_GPIOCOM5, |
Maulik V Vaghela | e3f030e | 2020-11-05 13:04:38 +0530 | [diff] [blame] | 164 | .first_pad = GPIO_COM5_START, |
| 165 | .last_pad = GPIO_COM5_END, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 166 | .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, |
| 167 | .pad_cfg_base = PAD_CFG_BASE, |
| 168 | .host_own_reg_0 = HOSTSW_OWN_REG_0, |
| 169 | .gpi_int_sts_reg_0 = GPI_INT_STS_0, |
| 170 | .gpi_int_en_reg_0 = GPI_INT_EN_0, |
Jonathon Hall | 397c150 | 2023-07-21 13:33:59 -0400 | [diff] [blame] | 171 | .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0, |
| 172 | .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 173 | .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, |
| 174 | .gpi_smi_en_reg_0 = GPI_SMI_EN_0, |
Michael Niewöhner | 85610d8 | 2020-11-23 22:02:20 +0100 | [diff] [blame] | 175 | .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, |
| 176 | .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 177 | .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, |
| 178 | .name = "GPP_G", |
| 179 | .acpi_path = "\\_SB.PCI0.GPIO", |
| 180 | .reset_map = rst_map, |
| 181 | .num_reset_vals = ARRAY_SIZE(rst_map), |
| 182 | .groups = jsl_community5_groups, |
| 183 | .num_groups = ARRAY_SIZE(jsl_community5_groups), |
| 184 | } |
| 185 | }; |
| 186 | |
| 187 | const struct pad_community *soc_gpio_get_community(size_t *num_communities) |
| 188 | { |
| 189 | *num_communities = ARRAY_SIZE(jsl_communities); |
| 190 | return jsl_communities; |
| 191 | } |
| 192 | |
| 193 | const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) |
| 194 | { |
| 195 | static const struct pmc_to_gpio_route routes[] = { |
| 196 | { PMC_GPP_A, GPP_A }, |
| 197 | { PMC_GPP_B, GPP_B }, |
Meera Ravindranath | d980339 | 2020-07-21 19:12:53 +0530 | [diff] [blame] | 198 | { PMC_GPP_G, GPP_G }, |
| 199 | { PMC_GPP_C, GPP_C }, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 200 | { PMC_GPP_R, GPP_R }, |
| 201 | { PMC_GPP_D, GPP_D }, |
| 202 | { PMC_GPP_S, GPP_S }, |
| 203 | { PMC_GPP_H, GPP_H }, |
Meera Ravindranath | d980339 | 2020-07-21 19:12:53 +0530 | [diff] [blame] | 204 | { PMC_GPP_F, GPP_F }, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 205 | { PMC_GPD, GPP_GPD }, |
Meera Ravindranath | d980339 | 2020-07-21 19:12:53 +0530 | [diff] [blame] | 206 | { PMC_GPP_E, GPP_E } |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 207 | }; |
| 208 | |
| 209 | *num = ARRAY_SIZE(routes); |
| 210 | return routes; |
| 211 | } |