Angel Pons | fabfe9d | 2020-04-05 15:47:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | |
| 3 | #include <device/device.h> |
| 4 | #include <device/pci.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <fsp/util.h> |
Dinesh Gehlot | 4da8830 | 2023-01-17 05:46:33 +0000 | [diff] [blame] | 7 | #include <gpio.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 8 | #include <intelblocks/acpi.h> |
| 9 | #include <intelblocks/cfg.h> |
| 10 | #include <intelblocks/itss.h> |
Karthikeyan Ramasubramanian | f871278 | 2020-07-24 15:57:50 -0600 | [diff] [blame] | 11 | #include <intelblocks/pcie_rp.h> |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 12 | #include <intelblocks/systemagent.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 13 | #include <intelblocks/xdci.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 14 | #include <soc/intel/common/vbt.h> |
| 15 | #include <soc/itss.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/ramstage.h> |
| 18 | #include <soc/soc_chip.h> |
| 19 | |
Karthikeyan Ramasubramanian | f871278 | 2020-07-24 15:57:50 -0600 | [diff] [blame] | 20 | static const struct pcie_rp_group pch_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 21 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
Karthikeyan Ramasubramanian | f871278 | 2020-07-24 15:57:50 -0600 | [diff] [blame] | 22 | { 0 } |
| 23 | }; |
| 24 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 25 | #if CONFIG(HAVE_ACPI_TABLES) |
| 26 | const char *soc_acpi_name(const struct device *dev) |
| 27 | { |
| 28 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 29 | return "PCI0"; |
| 30 | |
| 31 | if (dev->path.type == DEVICE_PATH_USB) { |
| 32 | switch (dev->path.usb.port_type) { |
| 33 | case 0: |
| 34 | /* Root Hub */ |
| 35 | return "RHUB"; |
| 36 | case 2: |
| 37 | /* USB2 ports */ |
| 38 | switch (dev->path.usb.port_id) { |
| 39 | case 0: return "HS01"; |
| 40 | case 1: return "HS02"; |
| 41 | case 2: return "HS03"; |
| 42 | case 3: return "HS04"; |
| 43 | case 4: return "HS05"; |
| 44 | case 5: return "HS06"; |
| 45 | case 6: return "HS07"; |
| 46 | case 7: return "HS08"; |
| 47 | case 8: return "HS09"; |
| 48 | case 9: return "HS10"; |
| 49 | } |
| 50 | break; |
| 51 | case 3: |
| 52 | /* USB3 ports */ |
| 53 | switch (dev->path.usb.port_id) { |
| 54 | case 0: return "SS01"; |
| 55 | case 1: return "SS02"; |
| 56 | case 2: return "SS03"; |
| 57 | case 3: return "SS04"; |
Reka Norman | a56fad6 | 2023-09-14 14:29:01 +1000 | [diff] [blame] | 58 | case 4: return "SS05"; |
| 59 | case 5: return "SS06"; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 60 | } |
| 61 | break; |
| 62 | } |
| 63 | return NULL; |
| 64 | } |
| 65 | if (dev->path.type != DEVICE_PATH_PCI) |
| 66 | return NULL; |
| 67 | |
| 68 | switch (dev->path.pci.devfn) { |
| 69 | case SA_DEVFN_ROOT: return "MCHC"; |
Tim Wawrzynczak | 4b74814 | 2020-06-29 12:34:55 -0600 | [diff] [blame] | 70 | case SA_DEVFN_IPU: return "IPU0"; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 71 | case PCH_DEVFN_ISH: return "ISHB"; |
Matt DeVillier | ecf2b42 | 2023-08-31 10:06:00 -0500 | [diff] [blame] | 72 | case SA_DEVFN_GNA: return "GNA"; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 73 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 74 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 75 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 76 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 77 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 78 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 79 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 80 | case PCH_DEVFN_SATA: return "SATA"; |
| 81 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 82 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 83 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 84 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 85 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 86 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 87 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 88 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 89 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 90 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 91 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 92 | case PCH_DEVFN_PCIE12: return "RP12"; |
| 93 | case PCH_DEVFN_UART0: return "UAR0"; |
| 94 | case PCH_DEVFN_UART1: return "UAR1"; |
| 95 | case PCH_DEVFN_UART2: return "UAR2"; |
| 96 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 97 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 98 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 99 | case PCH_DEVFN_GSPI3: return "SPI3"; |
Karthikeyan Ramasubramanian | e5ec91b | 2020-04-15 14:27:36 -0600 | [diff] [blame] | 100 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 101 | case PCH_DEVFN_SDCARD: return "SDXC"; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 102 | case PCH_DEVFN_HDA: return "HDAS"; |
| 103 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 104 | case PCH_DEVFN_GBE: return "GLAN"; |
| 105 | } |
| 106 | |
| 107 | return NULL; |
| 108 | } |
| 109 | #endif |
| 110 | |
Angel Pons | 73a22ed | 2021-04-05 12:26:51 +0200 | [diff] [blame] | 111 | /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 112 | static void soc_fill_gpio_pm_configuration(void) |
| 113 | { |
| 114 | uint8_t value[TOTAL_GPIO_COMM]; |
| 115 | const config_t *config = config_of_soc(); |
| 116 | |
| 117 | if (config->gpio_override_pm) |
Angel Pons | 0c0d492 | 2021-04-05 13:02:45 +0200 | [diff] [blame] | 118 | memcpy(value, config->gpio_pm, sizeof(value)); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 119 | else |
Angel Pons | 0c0d492 | 2021-04-05 13:02:45 +0200 | [diff] [blame] | 120 | memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 121 | |
| 122 | gpio_pm_configure(value, TOTAL_GPIO_COMM); |
| 123 | } |
| 124 | |
| 125 | void soc_init_pre_device(void *chip_info) |
| 126 | { |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 127 | /* Perform silicon specific init. */ |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 128 | fsp_silicon_init(); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 129 | |
| 130 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 131 | fsp_display_fvi_version_hob(); |
| 132 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 133 | soc_fill_gpio_pm_configuration(); |
Karthikeyan Ramasubramanian | f871278 | 2020-07-24 15:57:50 -0600 | [diff] [blame] | 134 | |
| 135 | /* swap enabled PCI ports in device tree if needed */ |
| 136 | pcie_rp_update_devicetree(pch_rp_groups); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 137 | } |
| 138 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 139 | static struct device_operations pci_domain_ops = { |
| 140 | .read_resources = &pci_domain_read_resources, |
| 141 | .set_resources = &pci_domain_set_resources, |
Arthur Heymans | 0b0113f | 2023-08-31 17:09:28 +0200 | [diff] [blame] | 142 | .scan_bus = &pci_host_bridge_scan_bus, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 143 | #if CONFIG(HAVE_ACPI_TABLES) |
| 144 | .acpi_name = &soc_acpi_name, |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 145 | .acpi_fill_ssdt = ssdt_set_above_4g_pci, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 146 | #endif |
| 147 | }; |
| 148 | |
| 149 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 150 | .read_resources = noop_read_resources, |
| 151 | .set_resources = noop_set_resources, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 152 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 153 | .acpi_fill_ssdt = generate_cpu_entries, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 154 | #endif |
| 155 | }; |
| 156 | |
Tim Wawrzynczak | c47422d | 2020-06-01 17:03:41 -0600 | [diff] [blame] | 157 | extern struct device_operations pmc_ops; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 158 | static void soc_enable(struct device *dev) |
| 159 | { |
| 160 | /* Set the operations if it is a special bus type */ |
| 161 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 162 | dev->ops = &pci_domain_ops; |
| 163 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 164 | dev->ops = &cpu_bus_ops; |
Tim Wawrzynczak | c47422d | 2020-06-01 17:03:41 -0600 | [diff] [blame] | 165 | else if (dev->path.type == DEVICE_PATH_PCI && |
| 166 | dev->path.pci.devfn == PCH_DEVFN_PMC) |
| 167 | dev->ops = &pmc_ops; |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 168 | else if (dev->path.type == DEVICE_PATH_GPIO) |
| 169 | block_gpio_enable(dev); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 170 | } |
| 171 | |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 172 | struct chip_operations soc_intel_jasperlake_ops = { |
Nicholas Sudsgaard | bfb11be | 2024-01-30 09:53:46 +0900 | [diff] [blame^] | 173 | .name = "Intel Jasperlake", |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 174 | .enable_dev = &soc_enable, |
| 175 | .init = &soc_init_pre_device, |
| 176 | }; |