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review.coreboot.org / coreboot / 2f8ba69b0ee5deafa9bad20c2a7b2b4785fcb565 / . / src / soc / intel / jasperlake / chip.c
blob: 7b53e17bd29498077de70a53c34cd23d856d1938 [file] [log] [blame]
Angel Ponsfabfe9d2020-04-05 15:47:07 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Aamir Bohradd7acaa2020-03-25 11:36:22 +0530[diff] [blame]3
4#include <device/device.h>
5#include <device/pci.h>
6#include <fsp/api.h>
7#include <fsp/util.h>
8#include <intelblocks/acpi.h>
9#include <intelblocks/cfg.h>
10#include <intelblocks/itss.h>
11#include <intelblocks/xdci.h>
12#include <romstage_handoff.h>
13#include <soc/intel/common/vbt.h>
14#include <soc/itss.h>
15#include <soc/pci_devs.h>
16#include <soc/ramstage.h>
17#include <soc/soc_chip.h>
18
19#if CONFIG(HAVE_ACPI_TABLES)
20const char *soc_acpi_name(const struct device *dev)
21{
22 if (dev->path.type == DEVICE_PATH_DOMAIN)
23 return "PCI0";
24
25 if (dev->path.type == DEVICE_PATH_USB) {
26 switch (dev->path.usb.port_type) {
27 case 0:
28 /* Root Hub */
29 return "RHUB";
30 case 2:
31 /* USB2 ports */
32 switch (dev->path.usb.port_id) {
33 case 0: return "HS01";
34 case 1: return "HS02";
35 case 2: return "HS03";
36 case 3: return "HS04";
37 case 4: return "HS05";
38 case 5: return "HS06";
39 case 6: return "HS07";
40 case 7: return "HS08";
41 case 8: return "HS09";
42 case 9: return "HS10";
43 }
44 break;
45 case 3:
46 /* USB3 ports */
47 switch (dev->path.usb.port_id) {
48 case 0: return "SS01";
49 case 1: return "SS02";
50 case 2: return "SS03";
51 case 3: return "SS04";
52 }
53 break;
54 }
55 return NULL;
56 }
57 if (dev->path.type != DEVICE_PATH_PCI)
58 return NULL;
59
60 switch (dev->path.pci.devfn) {
61 case SA_DEVFN_ROOT: return "MCHC";
62 case PCH_DEVFN_ISH: return "ISHB";
63 case PCH_DEVFN_XHCI: return "XHCI";
64 case PCH_DEVFN_I2C0: return "I2C0";
65 case PCH_DEVFN_I2C1: return "I2C1";
66 case PCH_DEVFN_I2C2: return "I2C2";
67 case PCH_DEVFN_I2C3: return "I2C3";
68 case PCH_DEVFN_I2C4: return "I2C4";
69 case PCH_DEVFN_I2C5: return "I2C5";
70 case PCH_DEVFN_SATA: return "SATA";
71 case PCH_DEVFN_PCIE1: return "RP01";
72 case PCH_DEVFN_PCIE2: return "RP02";
73 case PCH_DEVFN_PCIE3: return "RP03";
74 case PCH_DEVFN_PCIE4: return "RP04";
75 case PCH_DEVFN_PCIE5: return "RP05";
76 case PCH_DEVFN_PCIE6: return "RP06";
77 case PCH_DEVFN_PCIE7: return "RP07";
78 case PCH_DEVFN_PCIE8: return "RP08";
79 case PCH_DEVFN_PCIE9: return "RP09";
80 case PCH_DEVFN_PCIE10: return "RP10";
81 case PCH_DEVFN_PCIE11: return "RP11";
82 case PCH_DEVFN_PCIE12: return "RP12";
83 case PCH_DEVFN_UART0: return "UAR0";
84 case PCH_DEVFN_UART1: return "UAR1";
85 case PCH_DEVFN_UART2: return "UAR2";
86 case PCH_DEVFN_GSPI0: return "SPI0";
87 case PCH_DEVFN_GSPI1: return "SPI1";
88 case PCH_DEVFN_GSPI2: return "SPI2";
89 case PCH_DEVFN_GSPI3: return "SPI3";
90 /* Keeping ACPI device name coherent with ec.asl */
91 case PCH_DEVFN_ESPI: return "LPCB";
92 case PCH_DEVFN_HDA: return "HDAS";
93 case PCH_DEVFN_SMBUS: return "SBUS";
94 case PCH_DEVFN_GBE: return "GLAN";
95 }
96
97 return NULL;
98}
99#endif
100
101/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
102static void soc_fill_gpio_pm_configuration(void)
103{
104 uint8_t value[TOTAL_GPIO_COMM];
105 const config_t *config = config_of_soc();
106
107 if (config->gpio_override_pm)
108 memcpy(value, config->gpio_pm, sizeof(uint8_t) *
109 TOTAL_GPIO_COMM);
110 else
111 memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
112 TOTAL_GPIO_COMM);
113
114 gpio_pm_configure(value, TOTAL_GPIO_COMM);
115}
116
117void soc_init_pre_device(void *chip_info)
118{
119 /* Snapshot the current GPIO IRQ polarities. FSP is setting a
120 * default policy that doesn't honor boards' requirements. */
121 itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
122
123 /* Perform silicon specific init. */
124 fsp_silicon_init(romstage_handoff_is_resume());
125
126 /* Display FIRMWARE_VERSION_INFO_HOB */
127 fsp_display_fvi_version_hob();
128
129 /* Restore GPIO IRQ polarities back to previous settings. */
130 itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
131
132 soc_fill_gpio_pm_configuration();
133}
134
135static void pci_domain_set_resources(struct device *dev)
136{
137 assign_resources(dev->link_list);
138}
139
140static struct device_operations pci_domain_ops = {
141 .read_resources = &pci_domain_read_resources,
142 .set_resources = &pci_domain_set_resources,
143 .scan_bus = &pci_domain_scan_bus,
144#if CONFIG(HAVE_ACPI_TABLES)
145 .acpi_name = &soc_acpi_name,
146#endif
147};
148
149static struct device_operations cpu_bus_ops = {
Nico Huber2f8ba692020-04-05 14:05:24 +0200[diff] [blame^]150 .read_resources = noop_read_resources,
151 .set_resources = noop_set_resources,
Aamir Bohradd7acaa2020-03-25 11:36:22 +0530[diff] [blame]152#if CONFIG(HAVE_ACPI_TABLES)
Nico Huber68680dd2020-03-31 17:34:52 +0200[diff] [blame]153 .acpi_fill_ssdt = generate_cpu_entries,
Aamir Bohradd7acaa2020-03-25 11:36:22 +0530[diff] [blame]154#endif
155};
156
157static void soc_enable(struct device *dev)
158{
159 /* Set the operations if it is a special bus type */
160 if (dev->path.type == DEVICE_PATH_DOMAIN)
161 dev->ops = &pci_domain_ops;
162 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
163 dev->ops = &cpu_bus_ops;
164}
165
Aamir Bohra512b77a2020-03-25 13:20:34 +0530[diff] [blame]166struct chip_operations soc_intel_jasperlake_ops = {
167 CHIP_NAME("Intel Jasperlake")
Aamir Bohradd7acaa2020-03-25 11:36:22 +0530[diff] [blame]168 .enable_dev = &soc_enable,
169 .init = &soc_init_pre_device,
170};