Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 2 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 3 | #include <console/console.h> |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 4 | #include <cf9_reset.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Kyösti Mälkki | 4ce0a07 | 2021-02-17 18:10:49 +0200 | [diff] [blame] | 6 | #include <romstage_handoff.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 7 | #include "sandybridge.h" |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 8 | #include <arch/romstage.h> |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 9 | #include <device/pci_def.h> |
| 10 | #include <device/device.h> |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 11 | #include <northbridge/intel/sandybridge/chip.h> |
Michał Żygowski | 68ff337 | 2021-11-21 13:47:25 +0100 | [diff] [blame] | 12 | #include <security/intel/txt/txt.h> |
| 13 | #include <security/intel/txt/txt_platform.h> |
| 14 | #include <security/intel/txt/txt_register.h> |
Elyes HAOUAS | 21b71ce6 | 2018-06-16 18:43:52 +0200 | [diff] [blame] | 15 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e2f0a5f | 2019-03-24 14:47:47 +0100 | [diff] [blame] | 16 | #include <southbridge/intel/common/pmclib.h> |
Patrick Rudolph | 9005071 | 2019-03-25 09:53:23 +0100 | [diff] [blame] | 17 | #include <elog.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 18 | |
Angel Pons | 9d8dac0 | 2022-04-09 08:34:29 +0200 | [diff] [blame] | 19 | __weak void mainboard_early_init(int s3resume) |
| 20 | { |
| 21 | } |
| 22 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 23 | __weak void mainboard_late_rcba_config(void) |
| 24 | { |
| 25 | } |
| 26 | |
Michał Żygowski | 68ff337 | 2021-11-21 13:47:25 +0100 | [diff] [blame] | 27 | static void configure_dpr(void) |
| 28 | { |
| 29 | union dpr_register dpr = txt_get_chipset_dpr(); |
| 30 | |
| 31 | /* |
| 32 | * Just need to program the size of DPR, enable and lock it. |
| 33 | * The dpr.top will always point to TSEG_BASE (updated by hardware). |
| 34 | * We do it early because it will be needed later to calculate cbmem_top. |
| 35 | */ |
| 36 | dpr.lock = 1; |
| 37 | dpr.epm = 1; |
| 38 | dpr.size = CONFIG_INTEL_TXT_DPR_SIZE; |
| 39 | pci_write_config32(HOST_BRIDGE, DPR, dpr.raw); |
| 40 | } |
| 41 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 42 | static void early_pch_reset_pmcon(void) |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 43 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 44 | /* Reset RTC power status */ |
Angel Pons | 9733f6a | 2020-06-07 19:23:03 +0200 | [diff] [blame] | 45 | pci_and_config8(PCH_LPC_DEV, GEN_PMCON_3, ~(1 << 2)); |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 46 | } |
| 47 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 48 | /* The romstage entry point for this platform is not mainboard-specific, hence the name */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 49 | void mainboard_romstage_entry(void) |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 50 | { |
| 51 | int s3resume = 0; |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 52 | |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 53 | if (mchbar_read16(SSKPD_HI) == 0xcafe) |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 54 | system_reset(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 55 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 56 | /* Init LPC, GPIO, BARs, disable watchdog ... */ |
| 57 | early_pch_init(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 58 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 59 | /* When using MRC, USB is initialized by MRC */ |
Julius Werner | 5d1f9a0 | 2019-03-07 17:07:26 -0800 | [diff] [blame] | 60 | if (CONFIG(USE_NATIVE_RAMINIT)) { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 61 | early_usb_init(mainboard_usb_ports); |
| 62 | } |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 63 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 64 | /* Perform some early chipset init needed before RAM initialization can work */ |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 65 | systemagent_early_init(); |
| 66 | printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 67 | |
| 68 | s3resume = southbridge_detect_s3_resume(); |
| 69 | |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame] | 70 | elog_boot_notify(s3resume); |
Patrick Rudolph | 9005071 | 2019-03-25 09:53:23 +0100 | [diff] [blame] | 71 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 72 | post_code(0x38); |
Vladimir Serbinenko | 609bd94 | 2016-01-31 14:00:54 +0100 | [diff] [blame] | 73 | |
Angel Pons | 9d8dac0 | 2022-04-09 08:34:29 +0200 | [diff] [blame] | 74 | mainboard_early_init(s3resume); |
| 75 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 76 | post_code(0x39); |
| 77 | |
Michał Żygowski | 68ff337 | 2021-11-21 13:47:25 +0100 | [diff] [blame] | 78 | if (CONFIG(INTEL_TXT)) { |
| 79 | configure_dpr(); |
| 80 | intel_txt_romstage_init(); |
| 81 | } |
| 82 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 83 | perform_raminit(s3resume); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 84 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 85 | post_code(0x3b); |
| 86 | /* Perform some initialization that must run before stage2 */ |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 87 | early_pch_reset_pmcon(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 88 | post_code(0x3c); |
| 89 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 90 | southbridge_configure_default_intmap(); |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 91 | southbridge_rcba_config(); |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 92 | mainboard_late_rcba_config(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 93 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 94 | post_code(0x3d); |
| 95 | |
Kyösti Mälkki | 4ce0a07 | 2021-02-17 18:10:49 +0200 | [diff] [blame] | 96 | northbridge_romstage_finalize(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 97 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 98 | post_code(0x3f); |
Kyösti Mälkki | 4ce0a07 | 2021-02-17 18:10:49 +0200 | [diff] [blame] | 99 | |
| 100 | romstage_handoff_init(s3resume); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 101 | } |