Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <stdint.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 16 | #include <console/console.h> |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 17 | #include <cf9_reset.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 19 | #include <cpu/x86/lapic.h> |
| 20 | #include <timestamp.h> |
| 21 | #include "sandybridge.h" |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 22 | #include <arch/romstage.h> |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 23 | #include <device/pci_def.h> |
| 24 | #include <device/device.h> |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 25 | #include <northbridge/intel/sandybridge/chip.h> |
Elyes HAOUAS | 21b71ce6 | 2018-06-16 18:43:52 +0200 | [diff] [blame] | 26 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e2f0a5f | 2019-03-24 14:47:47 +0100 | [diff] [blame] | 27 | #include <southbridge/intel/common/pmclib.h> |
Patrick Rudolph | 9005071 | 2019-03-25 09:53:23 +0100 | [diff] [blame] | 28 | #include <elog.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 29 | |
Arthur Heymans | dc2e7c6 | 2019-11-12 16:17:26 +0100 | [diff] [blame] | 30 | __weak void mainboard_early_init(int s3_resume) |
| 31 | { |
| 32 | } |
| 33 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 34 | __weak void mainboard_late_rcba_config(void) |
| 35 | { |
| 36 | } |
| 37 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 38 | static void early_pch_reset_pmcon(void) |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 39 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 40 | u8 reg8; |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 41 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame^] | 42 | /* Reset RTC power status */ |
Patrick Rudolph | 5c31af8 | 2017-05-03 17:47:54 +0200 | [diff] [blame] | 43 | reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 44 | reg8 &= ~(1 << 2); |
Patrick Rudolph | 5c31af8 | 2017-05-03 17:47:54 +0200 | [diff] [blame] | 45 | pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 46 | } |
| 47 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame^] | 48 | /* The romstage entry point for this platform is not mainboard-specific, hence the name */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 49 | void mainboard_romstage_entry(void) |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 50 | { |
| 51 | int s3resume = 0; |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 52 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame^] | 53 | if (MCHBAR16(SSKPD_HI) == 0xCAFE) |
Elyes HAOUAS | 1bc7b6e | 2019-05-05 16:29:41 +0200 | [diff] [blame] | 54 | system_reset(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 55 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 56 | enable_lapic(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 57 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 58 | /* Init LPC, GPIO, BARs, disable watchdog ... */ |
| 59 | early_pch_init(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 60 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame^] | 61 | /* When using MRC, USB is initialized by MRC */ |
Julius Werner | 5d1f9a0 | 2019-03-07 17:07:26 -0800 | [diff] [blame] | 62 | if (CONFIG(USE_NATIVE_RAMINIT)) { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 63 | early_usb_init(mainboard_usb_ports); |
| 64 | } |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 65 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame^] | 66 | /* Perform some early chipset init needed before RAM initialization can work */ |
Patrick Rudolph | 2cdb65d | 2019-03-24 18:08:43 +0100 | [diff] [blame] | 67 | systemagent_early_init(); |
| 68 | printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 69 | |
| 70 | s3resume = southbridge_detect_s3_resume(); |
| 71 | |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame] | 72 | elog_boot_notify(s3resume); |
Patrick Rudolph | 9005071 | 2019-03-25 09:53:23 +0100 | [diff] [blame] | 73 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 74 | post_code(0x38); |
Vladimir Serbinenko | 609bd94 | 2016-01-31 14:00:54 +0100 | [diff] [blame] | 75 | |
| 76 | mainboard_early_init(s3resume); |
| 77 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 78 | post_code(0x39); |
| 79 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 80 | perform_raminit(s3resume); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 81 | |
| 82 | timestamp_add_now(TS_AFTER_INITRAM); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 83 | |
| 84 | post_code(0x3b); |
| 85 | /* Perform some initialization that must run before stage2 */ |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 86 | early_pch_reset_pmcon(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 87 | post_code(0x3c); |
| 88 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 89 | southbridge_configure_default_intmap(); |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 90 | southbridge_rcba_config(); |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 91 | mainboard_late_rcba_config(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 92 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 93 | post_code(0x3d); |
| 94 | |
| 95 | northbridge_romstage_finalize(s3resume); |
| 96 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 97 | post_code(0x3f); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 98 | } |