Patrick Georgi | d1e50f9 | 2020-03-04 15:00:05 +0100 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 2 | |
Jonathan Neuschäfer | 2764919 | 2018-02-13 14:01:22 +0100 | [diff] [blame] | 3 | ################################################################################ |
| 4 | ## RISC-V specific options |
| 5 | ################################################################################ |
Martin Roth | 202e7d4 | 2018-07-18 12:03:48 -0600 | [diff] [blame] | 6 | ifeq ($(CONFIG_ARCH_RISCV),y) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 7 | |
Julius Werner | fffee87 | 2016-03-07 17:55:43 -0800 | [diff] [blame] | 8 | ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) |
| 9 | check-ramstage-overlap-regions += stack |
| 10 | endif |
| 11 | |
Jonathan Neuschäfer | 6dff3fd | 2018-09-30 20:09:58 +0200 | [diff] [blame] | 12 | riscv_flags = -I$(src)/arch/riscv/ |
Ronald G. Minnich | 0535804 | 2018-12-19 17:52:43 -0800 | [diff] [blame] | 13 | |
| 14 | ifeq ($(CONFIG_ARCH_RISCV_RV64),y) |
| 15 | _rv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64 |
| 16 | else |
| 17 | ifeq ($(CONFIG_ARCH_RISCV_RV32),y) |
| 18 | _rv_flags += -D__riscv -D__riscv_xlen=32 -D__riscv_flen=32 |
| 19 | else |
| 20 | $(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32") |
| 21 | endif |
| 22 | endif |
| 23 | |
Patrick Georgi | f0d5f67 | 2022-09-08 20:25:46 +0200 | [diff] [blame] | 24 | # Needed for -print-libgcc-file-name which gets confused about all those arch |
| 25 | # suffixes in ARCH_SUFFIX_riscv. |
| 26 | simple_riscv_flags = $(riscv_flags) |
| 27 | |
Arthur Heymans | 0d504c8 | 2023-04-19 21:24:04 +0200 | [diff] [blame] | 28 | ifeq ($(CONFIG_COMPILER_GCC),y) |
| 29 | MARCH_SUFFIX=$(ARCH_SUFFIX_riscv) |
| 30 | else |
| 31 | MARCH_SUFFIX= |
| 32 | endif |
| 33 | |
Jonathan Neuschäfer | 6dff3fd | 2018-09-30 20:09:58 +0200 | [diff] [blame] | 34 | ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) |
Arthur Heymans | 0d504c8 | 2023-04-19 21:24:04 +0200 | [diff] [blame] | 35 | riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) |
Patrick Georgi | f0d5f67 | 2022-09-08 20:25:46 +0200 | [diff] [blame] | 36 | simple_riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) |
Jonathan Neuschäfer | 6dff3fd | 2018-09-30 20:09:58 +0200 | [diff] [blame] | 37 | else |
Ronald G. Minnich | 0535804 | 2018-12-19 17:52:43 -0800 | [diff] [blame] | 38 | riscv_flags += $(_rv_flags) |
Patrick Georgi | f0d5f67 | 2022-09-08 20:25:46 +0200 | [diff] [blame] | 39 | simple_riscv_flags += $(_rv_flags) |
Jonathan Neuschäfer | 6dff3fd | 2018-09-30 20:09:58 +0200 | [diff] [blame] | 40 | endif |
Jonathan Neuschäfer | 2764919 | 2018-02-13 14:01:22 +0100 | [diff] [blame] | 41 | |
Arthur Heymans | 0d504c8 | 2023-04-19 21:24:04 +0200 | [diff] [blame] | 42 | riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI) |
Jonathan Neuschäfer | 2764919 | 2018-02-13 14:01:22 +0100 | [diff] [blame] | 43 | |
Patrick Georgi | f0d5f67 | 2022-09-08 20:25:46 +0200 | [diff] [blame] | 44 | COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(simple_riscv_flags) -print-libgcc-file-name) |
Jonathan Neuschäfer | 2764919 | 2018-02-13 14:01:22 +0100 | [diff] [blame] | 45 | |
Patrick Georgi | f0d5f67 | 2022-09-08 20:25:46 +0200 | [diff] [blame] | 46 | COMPILER_RT_romstage = $(shell $(GCC_romstage) $(simple_riscv_flags) -print-libgcc-file-name) |
Xiang Wang | 5fed693 | 2018-07-12 14:56:05 +0800 | [diff] [blame] | 47 | |
Patrick Georgi | f0d5f67 | 2022-09-08 20:25:46 +0200 | [diff] [blame] | 48 | COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(simple_riscv_flags) -print-libgcc-file-name) |
Jonathan Neuschäfer | 2764919 | 2018-02-13 14:01:22 +0100 | [diff] [blame] | 49 | |
Arthur Heymans | bf0b06d | 2022-05-13 14:49:44 +0200 | [diff] [blame^] | 50 | ## All stages |
| 51 | |
| 52 | all-y += trap_util.S |
| 53 | all-y += trap_handler.c |
| 54 | all-y += fp_asm.S |
| 55 | all-y += misaligned.c |
| 56 | all-y += sbi.c |
| 57 | all-y += mcall.c |
| 58 | all-y += virtual_memory.c |
| 59 | all-y += boot.c |
| 60 | all-y += smp.c |
| 61 | all-y += misc.c |
| 62 | all-$(ARCH_RISCV_PMP) += pmp.c |
| 63 | all-y += \ |
| 64 | $(top)/src/lib/memchr.c \ |
| 65 | $(top)/src/lib/memcmp.c \ |
| 66 | $(top)/src/lib/memcpy.c \ |
| 67 | $(top)/src/lib/memmove.c \ |
| 68 | $(top)/src/lib/memset.c |
| 69 | all-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c |
| 70 | |
| 71 | |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 72 | ################################################################################ |
| 73 | ## bootblock |
| 74 | ################################################################################ |
| 75 | ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) |
| 76 | |
Xiang Wang | 07bc325 | 2018-07-20 16:16:46 +0800 | [diff] [blame] | 77 | bootblock-y = bootblock.S |
Philipp Hug | 199b75f | 2018-09-13 18:11:56 +0200 | [diff] [blame] | 78 | |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 79 | $(objcbfs)/bootblock.debug: $$(bootblock-objs) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 80 | @printf " LINK $(subst $(obj)/,,$(@))\n" |
Aaron Durbin | d4dd44c | 2015-09-06 10:15:17 -0500 | [diff] [blame] | 81 | $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 82 | -T $(call src-to-obj,bootblock,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ |
Patrick Georgi | 3332f33 | 2015-07-18 00:25:12 +0200 | [diff] [blame] | 83 | $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 84 | |
Jonathan Neuschäfer | 1282b8d | 2016-06-10 19:35:15 +0200 | [diff] [blame] | 85 | bootblock-c-ccopts += $(riscv_flags) |
| 86 | bootblock-S-ccopts += $(riscv_asm_flags) |
| 87 | |
Philipp Hug | b09e500 | 2019-02-06 06:48:51 +0100 | [diff] [blame] | 88 | ifeq ($(CONFIG_ARCH_RISCV_RV32),y) |
| 89 | LDFLAGS_bootblock += -m elf32lriscv |
| 90 | endif #CONFIG_ARCH_RISCV_RV32 |
| 91 | |
Martin Roth | 202e7d4 | 2018-07-18 12:03:48 -0600 | [diff] [blame] | 92 | endif #CONFIG_ARCH_BOOTBLOCK_RISCV |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 93 | |
| 94 | ################################################################################ |
| 95 | ## romstage |
| 96 | ################################################################################ |
| 97 | ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) |
| 98 | |
Nico Huber | c01d092 | 2019-11-04 16:32:01 +0100 | [diff] [blame] | 99 | romstage-y += romstage.c |
Philipp Hug | 199b75f | 2018-09-13 18:11:56 +0200 | [diff] [blame] | 100 | |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 101 | # Build the romstage |
| 102 | |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 103 | $(objcbfs)/romstage.debug: $$(romstage-objs) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 104 | @printf " LINK $(subst $(obj)/,,$(@))\n" |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 105 | $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 106 | |
| 107 | romstage-c-ccopts += $(riscv_flags) |
| 108 | romstage-S-ccopts += $(riscv_asm_flags) |
| 109 | |
Philipp Hug | b09e500 | 2019-02-06 06:48:51 +0100 | [diff] [blame] | 110 | ifeq ($(CONFIG_ARCH_RISCV_RV32),y) |
| 111 | LDFLAGS_romstage += -m elf32lriscv |
| 112 | endif #CONFIG_ARCH_RISCV_RV32 |
| 113 | |
Martin Roth | 202e7d4 | 2018-07-18 12:03:48 -0600 | [diff] [blame] | 114 | endif #CONFIG_ARCH_ROMSTAGE_RISCV |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 115 | |
| 116 | ################################################################################ |
| 117 | ## ramstage |
| 118 | ################################################################################ |
| 119 | ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) |
| 120 | |
| 121 | ramstage-y = |
Xiang Wang | 21ed107 | 2018-08-29 17:21:19 +0800 | [diff] [blame] | 122 | ramstage-y += ramstage.S |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 123 | ramstage-y += tables.c |
Xiang Wang | 820dcfc | 2018-07-19 17:35:39 +0800 | [diff] [blame] | 124 | ramstage-y += payload.c |
Jonathan Neuschäfer | 3a4511e | 2018-12-12 01:08:24 +0100 | [diff] [blame] | 125 | ramstage-y += fit_payload.c |
Philipp Hug | 199b75f | 2018-09-13 18:11:56 +0200 | [diff] [blame] | 126 | |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 127 | $(eval $(call create_class_compiler,rmodules,riscv)) |
| 128 | |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 129 | ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c |
| 130 | |
| 131 | # Build the ramstage |
| 132 | |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 133 | $(objcbfs)/ramstage.debug: $$(ramstage-objs) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 134 | @printf " CC $(subst $(obj)/,,$(@))\n" |
Furquan Shaikh | 46514c2 | 2020-06-11 11:59:07 -0700 | [diff] [blame] | 135 | $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE)) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 136 | |
| 137 | ramstage-c-ccopts += $(riscv_flags) |
| 138 | ramstage-S-ccopts += $(riscv_asm_flags) |
| 139 | |
Philipp Hug | b09e500 | 2019-02-06 06:48:51 +0100 | [diff] [blame] | 140 | ifeq ($(CONFIG_ARCH_RISCV_RV32),y) |
| 141 | LDFLAGS_ramstage += -m elf32lriscv |
| 142 | endif #CONFIG_ARCH_RISCV_RV32 |
| 143 | |
Martin Roth | 202e7d4 | 2018-07-18 12:03:48 -0600 | [diff] [blame] | 144 | endif #CONFIG_ARCH_RAMSTAGE_RISCV |
Xiang Wang | a6f9eab | 2019-03-28 12:19:30 +0800 | [diff] [blame] | 145 | |
| 146 | ifeq ($(CONFIG_RISCV_OPENSBI),y) |
| 147 | |
| 148 | OPENSBI_SOURCE := $(top)/3rdparty/opensbi |
| 149 | OPENSBI_BUILD := $(abspath $(obj)/3rdparty/opensbi) |
| 150 | OPENSBI_TARGET := $(OPENSBI_BUILD)/platform/$(CONFIG_OPENSBI_PLATFORM)/firmware/fw_dynamic.elf |
| 151 | OPENSBI := $(obj)/opensbi.elf |
| 152 | |
Arthur Heymans | cf827af | 2023-05-23 12:38:19 +0200 | [diff] [blame] | 153 | # TODO: Building with clang has troubles finding the proper linker. |
| 154 | # Always use GCC for now. |
Xiang Wang | a6f9eab | 2019-03-28 12:19:30 +0800 | [diff] [blame] | 155 | $(OPENSBI_TARGET): $(obj)/config.h | $(OPENSBI_SOURCE) |
| 156 | printf " MAKE $(subst $(obj)/,,$(@))\n" |
| 157 | mkdir -p $(OPENSBI_BUILD) |
| 158 | $(MAKE) \ |
| 159 | -C "$(OPENSBI_SOURCE)" \ |
Arthur Heymans | cf827af | 2023-05-23 12:38:19 +0200 | [diff] [blame] | 160 | CC="$(GCC_ramstage) -fno-builtin" \ |
Xiang Wang | a6f9eab | 2019-03-28 12:19:30 +0800 | [diff] [blame] | 161 | LD="$(LD_ramstage)" \ |
| 162 | OBJCOPY="$(OBJCOPY_ramstage)" \ |
| 163 | AR="$(AR_ramstage)" \ |
| 164 | PLATFORM=$(CONFIG_OPENSBI_PLATFORM) \ |
| 165 | O="$(OPENSBI_BUILD)" \ |
| 166 | FW_JUMP=y \ |
| 167 | FW_DYNAMIC=y \ |
| 168 | FW_PAYLOAD=n \ |
| 169 | FW_PAYLOAD_OFFSET=0 \ |
| 170 | FW_TEXT_START=$(CONFIG_OPENSBI_TEXT_START) |
| 171 | |
| 172 | $(OPENSBI): $(OPENSBI_TARGET) |
| 173 | cp $< $@ |
| 174 | |
| 175 | OPENSBI_CBFS := $(CONFIG_CBFS_PREFIX)/opensbi |
| 176 | $(OPENSBI_CBFS)-file := $(OPENSBI) |
| 177 | $(OPENSBI_CBFS)-type := payload |
| 178 | $(OPENSBI_CBFS)-compression := $(CBFS_COMPRESS_FLAG) |
| 179 | cbfs-files-y += $(OPENSBI_CBFS) |
| 180 | |
| 181 | check-ramstage-overlap-files += $(OPENSBI_CBFS) |
| 182 | |
| 183 | CPPFLAGS_common += -I$(OPENSBI_SOURCE)/include |
| 184 | ramstage-y += opensbi.c |
| 185 | |
| 186 | endif #CONFIG_RISCV_OPENSBI |
| 187 | |
Martin Roth | 202e7d4 | 2018-07-18 12:03:48 -0600 | [diff] [blame] | 188 | endif #CONFIG_ARCH_RISCV |