Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
Shaunak Saha | bd42780 | 2017-07-18 00:19:33 -0700 | [diff] [blame^] | 20 | #include <intelblocks/acpi.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 21 | #include <intelblocks/lpc_lib.h> |
Ravi Sarawadi | efa606b | 2017-08-04 16:26:09 -0700 | [diff] [blame] | 22 | #include <soc/pm.h> |
| 23 | |
| 24 | /* Common weak definition, needs to be implemented in each soc LPC driver. */ |
| 25 | __attribute__((weak)) void lpc_init(struct device *dev) { /* no-op */ } |
| 26 | |
| 27 | static void soc_lpc_add_io_resources(device_t dev) |
| 28 | { |
| 29 | struct resource *res; |
| 30 | |
| 31 | /* Add the default claimed legacy IO range for the LPC device. */ |
| 32 | res = new_resource(dev, 0); |
| 33 | res->base = 0; |
| 34 | res->size = 0x1000; |
| 35 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 36 | } |
| 37 | |
| 38 | static void soc_lpc_read_resources(device_t dev) |
| 39 | { |
| 40 | /* Get the PCI resources of this device. */ |
| 41 | pci_dev_read_resources(dev); |
| 42 | |
| 43 | /* Add IO resources to LPC. */ |
| 44 | soc_lpc_add_io_resources(dev); |
| 45 | } |
| 46 | |
| 47 | static void set_child_resources(struct device *dev); |
| 48 | |
| 49 | static void loop_resources(struct device *dev) |
| 50 | { |
| 51 | struct resource *res; |
| 52 | |
| 53 | for (res = dev->resource_list; res; res = res->next) { |
| 54 | if (res->flags & IORESOURCE_IO) |
| 55 | lpc_open_pmio_window(res->base, res->size); |
| 56 | |
| 57 | if (res->flags & IORESOURCE_MEM) { |
| 58 | /* Check if this is already decoded. */ |
| 59 | if (lpc_fits_fixed_mmio_window(res->base, res->size)) |
| 60 | continue; |
| 61 | |
| 62 | lpc_open_mmio_window(res->base, res->size); |
| 63 | } |
| 64 | } |
| 65 | set_child_resources(dev); |
| 66 | } |
| 67 | |
| 68 | /* |
| 69 | * Loop through all the child devices' resources, and open up windows to the |
| 70 | * LPC bus, as appropriate. |
| 71 | */ |
| 72 | static void set_child_resources(struct device *dev) |
| 73 | { |
| 74 | struct bus *link; |
| 75 | struct device *child; |
| 76 | |
| 77 | for (link = dev->link_list; link; link = link->next) { |
| 78 | for (child = link->children; child; child = child->sibling) |
| 79 | loop_resources(child); |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | static void set_resources(device_t dev) |
| 84 | { |
| 85 | pci_dev_set_resources(dev); |
| 86 | |
| 87 | /* Now open up windows to devices which have declared resources. */ |
| 88 | set_child_resources(dev); |
| 89 | } |
| 90 | |
| 91 | static struct device_operations device_ops = { |
| 92 | .read_resources = soc_lpc_read_resources, |
| 93 | .set_resources = set_resources, |
| 94 | .enable_resources = pci_dev_enable_resources, |
| 95 | .write_acpi_tables = southbridge_write_acpi_tables, |
| 96 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
| 97 | .init = lpc_init, |
| 98 | .scan_bus = scan_lpc_bus, |
| 99 | }; |
| 100 | |
| 101 | static const unsigned short pci_device_ids[] = { |
| 102 | PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE, |
| 103 | PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE, |
| 104 | PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, |
| 105 | PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, |
| 106 | PCI_DEVICE_ID_INTEL_KBP_H_C236, |
| 107 | PCI_DEVICE_ID_INTEL_KBP_H_PREMIUM, |
| 108 | PCI_DEVICE_ID_INTEL_KBP_H_QM170, |
| 109 | PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, |
| 110 | PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, |
| 111 | PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU, |
| 112 | PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM, |
| 113 | PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, |
| 114 | PCI_DEVICE_ID_INTEL_APL_LPC, |
| 115 | PCI_DEVICE_ID_INTEL_GLK_LPC, |
| 116 | 0 |
| 117 | }; |
| 118 | |
| 119 | static const struct pci_driver soc_lpc __pci_driver = { |
| 120 | .ops = &device_ops, |
| 121 | .vendor = PCI_VENDOR_ID_INTEL, |
| 122 | .devices = pci_device_ids, |
| 123 | }; |