Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 2 | |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 3 | #include <bootstate.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 4 | #include <commonlib/console/post_codes.h> |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 6 | #include <cpu/x86/smm.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 7 | #include <device/mmio.h> |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 8 | #include <device/pci.h> |
Michael Niewöhner | 305b648 | 2019-09-22 21:56:17 +0200 | [diff] [blame] | 9 | #include <intelblocks/cpulib.h> |
Matt DeVillier | 575a2e5 | 2022-02-10 17:01:35 -0600 | [diff] [blame] | 10 | #include <intelblocks/cse.h> |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 11 | #include <intelblocks/lpc_lib.h> |
| 12 | #include <intelblocks/pcr.h> |
Subrata Banik | 0359d9d | 2020-09-28 18:43:47 +0530 | [diff] [blame] | 13 | #include <intelblocks/pmclib.h> |
Tim Wawrzynczak | 9f0266c | 2021-08-26 09:17:53 -0600 | [diff] [blame] | 14 | #include <intelblocks/systemagent.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 15 | #include <intelblocks/tco.h> |
Sumeet Pawnikar | 810527a | 2019-07-23 22:02:16 +0530 | [diff] [blame] | 16 | #include <intelblocks/thermal.h> |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 17 | #include <soc/p2sb.h> |
| 18 | #include <soc/pci_devs.h> |
| 19 | #include <soc/pcr_ids.h> |
| 20 | #include <soc/pm.h> |
| 21 | #include <soc/smbus.h> |
| 22 | #include <soc/systemagent.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 23 | #include <spi-generic.h> |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 24 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 25 | #include "chip.h" |
| 26 | |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 27 | #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ |
| 28 | #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ |
| 29 | #define CAM_CLK_EN (1 << 1) |
| 30 | #define MIPI_CLK (1 << 0) |
| 31 | #define HDPLL_CLK (0 << 0) |
| 32 | |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 33 | static void pch_enable_isclk(void) |
| 34 | { |
| 35 | pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); |
| 36 | pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); |
| 37 | } |
| 38 | |
| 39 | static void pch_handle_sideband(config_t *config) |
| 40 | { |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 41 | if (config->pch_isclk) |
| 42 | pch_enable_isclk(); |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 43 | } |
| 44 | |
| 45 | static void pch_finalize(void) |
| 46 | { |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 47 | uint32_t reg32; |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 48 | uint8_t *pmcbase; |
| 49 | config_t *config; |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 50 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 51 | tco_lockdown(); |
Sumeet Pawnikar | 810527a | 2019-07-23 22:02:16 +0530 | [diff] [blame] | 52 | |
| 53 | /* |
| 54 | * Set low maximum temp threshold value used for dynamic thermal sensor |
| 55 | * shutdown consideration. |
| 56 | * |
| 57 | * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the |
| 58 | * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. |
| 59 | */ |
| 60 | pch_thermal_configuration(); |
| 61 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 62 | config = config_of_soc(); |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 63 | pmcbase = pmc_mmio_regs(); |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 64 | |
Michael Niewöhner | 4e8baf9 | 2020-10-04 14:34:41 +0200 | [diff] [blame] | 65 | if (config->s0ix_enable && config->cppmvric2_adsposcdis) { |
| 66 | /* Enable Audio DSP OSC qualification for S0ix */ |
| 67 | reg32 = read32(pmcbase + CPPMVRIC2); |
| 68 | reg32 &= ~ADSPOSCDIS; |
| 69 | write32(pmcbase + CPPMVRIC2, reg32); |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 70 | } |
| 71 | |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 72 | pch_handle_sideband(config); |
Krishna Prasad Bhat | 2de1903 | 2019-03-14 23:23:22 +0530 | [diff] [blame] | 73 | |
| 74 | pmc_clear_pmcon_sts(); |
Michael Niewöhner | 305b648 | 2019-09-22 21:56:17 +0200 | [diff] [blame] | 75 | |
| 76 | /* |
| 77 | * Lock chipset memory registers to protect SMM. |
| 78 | * When SkipMpInit=0, this is done by FSP. |
| 79 | */ |
| 80 | if (!CONFIG(USE_INTEL_FSP_MP_INIT)) |
| 81 | cpu_lt_lock_memory(); |
| 82 | |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | static void soc_finalize(void *unused) |
| 86 | { |
| 87 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
| 88 | |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 89 | pch_finalize(); |
Kyösti Mälkki | b658548 | 2020-06-01 15:11:14 +0300 | [diff] [blame] | 90 | apm_control(APM_CNT_FINALIZE); |
Matt DeVillier | 575a2e5 | 2022-02-10 17:01:35 -0600 | [diff] [blame] | 91 | if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && |
| 92 | CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) |
| 93 | heci1_disable(); |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 94 | |
| 95 | /* Indicate finalize step with post code */ |
| 96 | post_code(POST_OS_BOOT); |
| 97 | } |
| 98 | |
| 99 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 100 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |