soc/intel/cnl: switch to PMC/IPC for HECI disable on SOC_INTEL_COMETLAKE
Commit d6dbd933 [soc/intel/cannonlake: Use SBI msg to disable HECI1]
switched CNL-based mainboards from using FSP for HECI disablement to SBI
msg, but this causes google/hatch to hang when attempting to unhide p2sb
as part of disabling HECI1 via SBI during SMM, so switch to using
PMC/IPC method. SOC_INTEL_WHISKEYLAKE and SOC_INTEL_COFFEELAKE do not
support PMC disablement method, so they remain using SBI.
Test: build/boot google/hatch, verify HECI1 disabled via console log and
lspci in booted OS.
Change-Id: I06f0eb312b579af4a0fe826403374dcd99689d21
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 63749f9..5410377 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -7,6 +7,7 @@
#include <device/mmio.h>
#include <device/pci.h>
#include <intelblocks/cpulib.h>
+#include <intelblocks/cse.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
@@ -95,6 +96,9 @@
pch_finalize();
apm_control(APM_CNT_FINALIZE);
sa_finalize();
+ if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) &&
+ CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC))
+ heci1_disable();
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);