Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 3 | #include <arch/hlt.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 4 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <cpu/x86/cache.h> |
| 9 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | e31ec29 | 2019-08-10 17:27:01 +0300 | [diff] [blame] | 10 | #include <cpu/intel/em64t100_save_state.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 11 | #include <device/pci_def.h> |
| 12 | #include <elog.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 13 | #include <soc/nvs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/pm.h> |
| 16 | #include <spi-generic.h> |
| 17 | #include <stdint.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 18 | #include <soc/gpio.h> |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 19 | #include <smmstore.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | static int smm_initialized; |
| 22 | |
| 23 | int southbridge_io_trap_handler(int smif) |
| 24 | { |
| 25 | switch (smif) { |
| 26 | case 0x32: |
| 27 | printk(BIOS_DEBUG, "OS Init\n"); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 28 | /* |
| 29 | * gnvs->smif: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | * On success, the IO Trap Handler returns 0 |
| 31 | * On failure, the IO Trap Handler returns a value != 0 |
| 32 | */ |
| 33 | gnvs->smif = 0; |
| 34 | return 1; /* IO trap handled */ |
| 35 | } |
| 36 | |
| 37 | /* Not handled */ |
| 38 | return 0; |
| 39 | } |
| 40 | |
| 41 | void southbridge_smi_set_eos(void) |
| 42 | { |
| 43 | enable_smi(EOS); |
| 44 | } |
| 45 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 46 | static void busmaster_disable_on_bus(int bus) |
| 47 | { |
| 48 | int slot, func; |
| 49 | unsigned int val; |
| 50 | unsigned char hdr; |
| 51 | |
| 52 | for (slot = 0; slot < 0x20; slot++) { |
| 53 | for (func = 0; func < 8; func++) { |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 54 | u16 reg16; |
Elyes HAOUAS | c8a649c | 2018-06-10 23:36:44 +0200 | [diff] [blame] | 55 | pci_devfn_t dev = PCI_DEV(bus, slot, func); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 56 | |
| 57 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
| 58 | |
| 59 | if (val == 0xffffffff || val == 0x00000000 || |
| 60 | val == 0x0000ffff || val == 0xffff0000) |
| 61 | continue; |
| 62 | |
| 63 | /* Disable Bus Mastering for this one device */ |
Elyes HAOUAS | 066e61f | 2020-04-29 10:28:20 +0200 | [diff] [blame] | 64 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 65 | reg16 &= ~PCI_COMMAND_MASTER; |
| 66 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 67 | |
| 68 | /* If this is a bridge, then follow it. */ |
| 69 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 70 | hdr &= 0x7f; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 71 | if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 72 | unsigned int buses; |
| 73 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 74 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 75 | } |
| 76 | } |
| 77 | } |
| 78 | } |
| 79 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 80 | static void tristate_gpios(uint32_t val) |
| 81 | { |
| 82 | /* Tri-state eMMC */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 83 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_CMD_MMIO_OFFSET, val); |
| 84 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D0_MMIO_OFFSET, val); |
| 85 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D1_MMIO_OFFSET, val); |
| 86 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D2_MMIO_OFFSET, val); |
| 87 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D3_MMIO_OFFSET, val); |
| 88 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D4_SD_WE_MMIO_OFFSET, val); |
| 89 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D5_MMIO_OFFSET, val); |
| 90 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D6_MMIO_OFFSET, val); |
| 91 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val); |
| 92 | write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_RCLK_OFFSET, val); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 93 | |
| 94 | /* Tri-state HDMI */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 95 | write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SDA_MMIO_OFFSET, val); |
| 96 | write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val); |
Ravi Sarawadi | a5d9888 | 2015-08-11 14:06:15 -0700 | [diff] [blame] | 97 | |
| 98 | /* Tri-state CFIO 139 and 140 */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 99 | write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_139_MMIO_OFFSET, val); |
| 100 | write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 101 | } |
| 102 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 103 | static void southbridge_smi_sleep(void) |
| 104 | { |
| 105 | uint32_t reg32; |
| 106 | uint8_t slp_typ; |
| 107 | uint16_t pmbase = get_pmbase(); |
| 108 | |
| 109 | /* First, disable further SMIs */ |
| 110 | disable_smi(SLP_SMI_EN); |
| 111 | |
| 112 | /* Figure out SLP_TYP */ |
| 113 | reg32 = inl(pmbase + PM1_CNT); |
| 114 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 115 | slp_typ = acpi_sleep_from_pm1(reg32); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 116 | |
| 117 | /* Do any mainboard sleep handling */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 118 | mainboard_smi_sleep(slp_typ); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 119 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 120 | /* Log S3, S4, and S5 entry */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 121 | if (slp_typ >= ACPI_S3) |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 122 | elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); |
| 123 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 124 | /* Clear pending GPE events */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 125 | clear_gpe_status(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 126 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 127 | /* Next, do the deed. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 128 | switch (slp_typ) { |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 129 | case ACPI_S0: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 130 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 131 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 132 | case ACPI_S1: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 133 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 134 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 135 | case ACPI_S3: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 136 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 137 | |
| 138 | /* Invalidate the cache before going to S3 */ |
| 139 | wbinvd(); |
| 140 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 141 | case ACPI_S4: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 142 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 143 | break; |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 144 | case ACPI_S5: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 145 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 146 | |
| 147 | /* Disable all GPE */ |
| 148 | disable_all_gpe(); |
| 149 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 150 | /* Also iterates over all bridges on bus 0 */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 151 | busmaster_disable_on_bus(0); |
| 152 | break; |
| 153 | default: |
| 154 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 155 | break; |
| 156 | } |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 157 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 158 | /* Clear pending wake status bit to avoid immediate wake */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 159 | write32((void *)(0xfed88000 + 0x0200), read32((void *)(0xfed88000 + 0x0200))); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 160 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 161 | /* Tri-state specific GPIOS to avoid leakage during S3/S5 */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 162 | if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 163 | tristate_gpios(PAD_CONTROL_REG0_TRISTATE); |
| 164 | |
| 165 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 166 | * Write back to the SLP register to cause the originally intended event again. |
| 167 | * We need to set BIT13 (SLP_EN) though to make the sleep happen. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 168 | */ |
| 169 | enable_pm1_control(SLP_EN); |
| 170 | |
| 171 | /* Make sure to stop executing code here for S3/S4/S5 */ |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 172 | if (slp_typ >= ACPI_S3) |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 173 | hlt(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 174 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 175 | /* |
| 176 | * In most sleep states, the code flow of this function ends at |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 177 | * the line above. However, if we entered sleep state S1 and wake |
| 178 | * up again, we will continue to execute code in this function. |
| 179 | */ |
| 180 | reg32 = inl(pmbase + PM1_CNT); |
| 181 | if (reg32 & SCI_EN) { |
| 182 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 183 | disable_pm1_control(SLP_EN | SLP_TYP); |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 188 | * Look for Synchronous IO SMI and use save state from that core in case |
| 189 | * we are not running on the same core that initiated the IO transaction. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 190 | */ |
| 191 | static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) |
| 192 | { |
| 193 | em64t100_smm_state_save_area_t *state; |
| 194 | int node; |
| 195 | |
| 196 | /* Check all nodes looking for the one that issued the IO */ |
| 197 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
| 198 | state = smm_get_save_state(node); |
| 199 | |
| 200 | /* Check for Synchronous IO (bit0==1) */ |
| 201 | if (!(state->io_misc_info & (1 << 0))) |
| 202 | continue; |
| 203 | |
| 204 | /* Make sure it was a write (bit4==0) */ |
| 205 | if (state->io_misc_info & (1 << 4)) |
| 206 | continue; |
| 207 | |
| 208 | /* Check for APMC IO port */ |
| 209 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 210 | continue; |
| 211 | |
| 212 | /* Check AX against the requested command */ |
| 213 | if ((state->rax & 0xff) != cmd) |
| 214 | continue; |
| 215 | |
| 216 | return state; |
| 217 | } |
| 218 | |
| 219 | return NULL; |
| 220 | } |
| 221 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 222 | static void southbridge_smi_gsmi(void) |
| 223 | { |
| 224 | u32 *ret, *param; |
| 225 | uint8_t sub_command; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 226 | em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 227 | |
| 228 | if (!io_smi) |
| 229 | return; |
| 230 | |
| 231 | /* Command and return value in EAX */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 232 | ret = (u32 *)&io_smi->rax; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 233 | sub_command = (uint8_t)(*ret >> 8); |
| 234 | |
| 235 | /* Parameter buffer in EBX */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 236 | param = (u32 *)&io_smi->rbx; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 237 | |
| 238 | /* drivers/elog/gsmi.c */ |
| 239 | *ret = gsmi_exec(sub_command, param); |
| 240 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 241 | |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 242 | static void southbridge_smi_store(void) |
| 243 | { |
| 244 | u8 sub_command, ret; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 245 | em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 246 | uint32_t reg_ebx; |
| 247 | |
| 248 | if (!io_smi) |
| 249 | return; |
| 250 | /* Command and return value in EAX */ |
| 251 | sub_command = (io_smi->rax >> 8) & 0xff; |
| 252 | |
| 253 | /* Parameter buffer in EBX */ |
| 254 | reg_ebx = io_smi->rbx; |
| 255 | |
| 256 | /* drivers/smmstore/smi.c */ |
| 257 | ret = smmstore_exec(sub_command, (void *)reg_ebx); |
| 258 | io_smi->rax = ret; |
| 259 | } |
| 260 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 261 | static void southbridge_smi_apmc(void) |
| 262 | { |
| 263 | uint8_t reg8; |
| 264 | em64t100_smm_state_save_area_t *state; |
| 265 | |
| 266 | /* Emulate B2 register as the FADT / Linux expects it */ |
| 267 | |
| 268 | reg8 = inb(APM_CNT); |
| 269 | switch (reg8) { |
| 270 | case APM_CNT_CST_CONTROL: |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 271 | /* |
| 272 | * Calling this function seems to cause |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 273 | * some kind of race condition in Linux |
| 274 | * and causes a kernel oops |
| 275 | */ |
| 276 | printk(BIOS_DEBUG, "C-state control\n"); |
| 277 | break; |
| 278 | case APM_CNT_PST_CONTROL: |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 279 | /* |
| 280 | * Calling this function seems to cause |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 281 | * some kind of race condition in Linux |
| 282 | * and causes a kernel oops |
| 283 | */ |
| 284 | printk(BIOS_DEBUG, "P-state control\n"); |
| 285 | break; |
| 286 | case APM_CNT_ACPI_DISABLE: |
| 287 | disable_pm1_control(SCI_EN); |
| 288 | printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); |
| 289 | break; |
| 290 | case APM_CNT_ACPI_ENABLE: |
| 291 | enable_pm1_control(SCI_EN); |
| 292 | printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); |
| 293 | break; |
| 294 | case APM_CNT_GNVS_UPDATE: |
| 295 | if (smm_initialized) { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 296 | printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 297 | return; |
| 298 | } |
| 299 | state = smi_apmc_find_state_save(reg8); |
| 300 | if (state) { |
| 301 | /* EBX in the state save contains the GNVS pointer */ |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 302 | gnvs = (struct global_nvs *)((uint32_t)state->rbx); |
Patrick Rudolph | 9f8f115 | 2020-05-06 11:58:45 +0200 | [diff] [blame] | 303 | if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { |
| 304 | printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); |
| 305 | return; |
| 306 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 307 | smm_initialized = 1; |
| 308 | printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); |
| 309 | } |
| 310 | break; |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 311 | case APM_CNT_ELOG_GSMI: |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 312 | if (CONFIG(ELOG_GSMI)) |
| 313 | southbridge_smi_gsmi(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 314 | break; |
Matt DeVillier | aa3b5e29 | 2018-12-25 22:10:48 -0600 | [diff] [blame] | 315 | case APM_CNT_SMMSTORE: |
| 316 | if (CONFIG(SMMSTORE)) |
| 317 | southbridge_smi_store(); |
| 318 | break; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | mainboard_smi_apmc(reg8); |
| 322 | } |
| 323 | |
| 324 | static void southbridge_smi_pm1(void) |
| 325 | { |
| 326 | uint16_t pm1_sts = clear_pm1_status(); |
| 327 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 328 | /* While OSPM is not active, poweroff immediately on a power button event */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 329 | if (pm1_sts & PWRBTN_STS) { |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 330 | /* Power button pressed */ |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 331 | elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 332 | disable_pm1_control(-1UL); |
| 333 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
| 334 | } |
| 335 | } |
| 336 | |
| 337 | static void southbridge_smi_gpe0(void) |
| 338 | { |
| 339 | clear_gpe_status(); |
| 340 | } |
| 341 | |
| 342 | static void southbridge_smi_tco(void) |
| 343 | { |
| 344 | uint32_t tco_sts = clear_tco_status(); |
| 345 | |
| 346 | /* Any TCO event? */ |
| 347 | if (!tco_sts) |
| 348 | return; |
| 349 | |
| 350 | if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ |
| 351 | /* Handle TCO timeout */ |
| 352 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
| 353 | } |
| 354 | } |
| 355 | |
| 356 | static void southbridge_smi_periodic(void) |
| 357 | { |
| 358 | uint32_t reg32; |
| 359 | |
| 360 | reg32 = inl(get_pmbase() + SMI_EN); |
| 361 | |
| 362 | /* Are periodic SMIs enabled? */ |
| 363 | if ((reg32 & PERIODIC_EN) == 0) |
| 364 | return; |
| 365 | |
| 366 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 367 | } |
| 368 | |
| 369 | typedef void (*smi_handler_t)(void); |
| 370 | |
| 371 | static const smi_handler_t southbridge_smi[32] = { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 372 | NULL, /* [0] reserved */ |
| 373 | NULL, /* [1] reserved */ |
| 374 | NULL, /* [2] BIOS_STS */ |
| 375 | NULL, /* [3] LEGACY_USB_STS */ |
| 376 | southbridge_smi_sleep, /* [4] SLP_SMI_STS */ |
| 377 | southbridge_smi_apmc, /* [5] APM_STS */ |
| 378 | NULL, /* [6] SWSMI_TMR_STS */ |
| 379 | NULL, /* [7] reserved */ |
| 380 | southbridge_smi_pm1, /* [8] PM1_STS */ |
| 381 | southbridge_smi_gpe0, /* [9] GPE0_STS */ |
| 382 | NULL, /* [10] reserved */ |
| 383 | NULL, /* [11] reserved */ |
| 384 | NULL, /* [12] reserved */ |
| 385 | southbridge_smi_tco, /* [13] TCO_STS */ |
| 386 | southbridge_smi_periodic, /* [14] PERIODIC_STS */ |
| 387 | NULL, /* [15] SERIRQ_SMI_STS */ |
| 388 | NULL, /* [16] SMBUS_SMI_STS */ |
| 389 | NULL, /* [17] LEGACY_USB2_STS */ |
| 390 | NULL, /* [18] INTEL_USB2_STS */ |
| 391 | NULL, /* [19] reserved */ |
| 392 | NULL, /* [20] PCI_EXP_SMI_STS */ |
| 393 | NULL, /* [21] reserved */ |
| 394 | NULL, /* [22] reserved */ |
| 395 | NULL, /* [23] reserved */ |
| 396 | NULL, /* [24] reserved */ |
| 397 | NULL, /* [25] reserved */ |
| 398 | NULL, /* [26] SPI_STS */ |
| 399 | NULL, /* [27] reserved */ |
| 400 | NULL, /* [28] PUNIT */ |
| 401 | NULL, /* [29] GUNIT */ |
| 402 | NULL, /* [30] reserved */ |
| 403 | NULL /* [31] reserved */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 404 | }; |
| 405 | |
| 406 | void southbridge_smi_handler(void) |
| 407 | { |
| 408 | int i; |
| 409 | uint32_t smi_sts; |
| 410 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 411 | /* |
| 412 | * We need to clear the SMI status registers, or we won't see what's |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 413 | * happening in the following calls. |
| 414 | */ |
| 415 | smi_sts = clear_smi_status(); |
| 416 | |
| 417 | /* Call SMI sub handler for each of the status bits */ |
| 418 | for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { |
| 419 | if (!(smi_sts & (1 << i))) |
| 420 | continue; |
| 421 | |
| 422 | if (southbridge_smi[i] != NULL) { |
| 423 | southbridge_smi[i](); |
| 424 | } else { |
| 425 | printk(BIOS_DEBUG, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 426 | "SMI_STS[%d] occurred, but no handler available.\n", i); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 427 | } |
| 428 | } |
| 429 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 430 | /* |
| 431 | * The GPIO SMI events do not have a status bit in SMI_STS. Therefore, |
| 432 | * these events need to be cleared and checked unconditionally. |
| 433 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 434 | mainboard_smi_gpi(clear_alt_status()); |
| 435 | } |