Angel Pons | 5f1bf2f | 2020-04-03 01:21:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 3 | #include <bootblock_common.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 4 | #include <stdint.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 5 | #include <cf9_reset.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 6 | #include <device/pnp_ops.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 7 | #include <superio/winbond/common/winbond.h> |
| 8 | #include <superio/winbond/w83627dhg/w83627dhg.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 9 | #include <console/console.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 10 | #include <northbridge/intel/i945/i945.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 11 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 12 | #include <cpu/x86/msr.h> |
| 13 | #include <cpu/intel/speedstep.h> |
| 14 | #include <arch/cpu.h> |
| 15 | |
| 16 | #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) |
| 17 | #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) |
| 18 | |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 19 | /* |
| 20 | * BSEL0 is connected with GPIO32 |
| 21 | * BSEL1 is connected with GPIO33 with inversed logic |
| 22 | * BSEL2 is connected with GPIO55 |
| 23 | */ |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 24 | static int setup_sio_gpio(u8 bsel) |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 25 | { |
| 26 | int need_reset = 0; |
| 27 | u8 reg, old_reg; |
| 28 | |
| 29 | pnp_enter_ext_func_mode(GPIO_DEV); |
| 30 | pnp_set_logical_device(GPIO_DEV); |
| 31 | |
| 32 | reg = 0x9a; |
| 33 | old_reg = pnp_read_config(GPIO_DEV, 0x2c); |
| 34 | pnp_write_config(GPIO_DEV, 0x2c, reg); |
| 35 | need_reset = (reg != old_reg); |
| 36 | |
| 37 | pnp_write_config(GPIO_DEV, 0x30, 0x0e); |
| 38 | pnp_write_config(GPIO_DEV, 0xe0, 0xde); |
| 39 | pnp_write_config(GPIO_DEV, 0xf0, 0xf3); |
| 40 | pnp_write_config(GPIO_DEV, 0xf4, 0x80); |
| 41 | pnp_write_config(GPIO_DEV, 0xf5, 0x80); |
| 42 | |
| 43 | /* Invert GPIO33 */ |
| 44 | pnp_write_config(GPIO_DEV, 0xf2, 0x08); |
| 45 | |
| 46 | reg = (bsel & 3) << 2; |
| 47 | old_reg = pnp_read_config(GPIO_DEV, 0xf1); |
| 48 | pnp_write_config(GPIO_DEV, 0xf1, reg); |
| 49 | need_reset += ((reg & 0xc) != (old_reg & 0xc)); |
| 50 | |
| 51 | reg = (bsel >> 2) << 5; |
| 52 | old_reg = pnp_read_config(GPIO_DEV, 0xe1); |
| 53 | pnp_write_config(GPIO_DEV, 0xe1, reg); |
| 54 | need_reset += ((reg & 0x20) != (old_reg & 0x20)); |
| 55 | |
| 56 | pnp_exit_ext_func_mode(GPIO_DEV); |
| 57 | |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 58 | return need_reset; |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | static u8 msr_get_fsb(void) |
| 62 | { |
| 63 | u8 fsbcfg; |
| 64 | msr_t msr; |
| 65 | const u32 eax = cpuid_eax(1); |
| 66 | |
| 67 | /* Netburst */ |
| 68 | if (((eax >> 8) & 0xf) == 0xf) { |
Elyes HAOUAS | f6bbc60 | 2017-11-26 15:34:20 +0100 | [diff] [blame] | 69 | msr = rdmsr(MSR_EBC_FREQUENCY_ID); |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 70 | fsbcfg = (msr.lo >> 16) & 0x7; |
| 71 | } else { /* Intel Core 2 */ |
| 72 | msr = rdmsr(MSR_FSB_FREQ); |
| 73 | fsbcfg = msr.lo & 0x7; |
| 74 | } |
| 75 | |
| 76 | return fsbcfg; |
| 77 | } |
| 78 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 79 | void mainboard_late_rcba_config(void) |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 80 | { |
Elyes HAOUAS | 1374607 | 2019-12-08 11:34:24 +0100 | [diff] [blame] | 81 | /* Enable only PCIe Root Port Clock Gate */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 82 | RCBA32(CG) = 0x00000001; |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 83 | } |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 84 | |
| 85 | void mainboard_pre_raminit_config(int s3_resume) |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 86 | { |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 87 | u8 c_bsel = msr_get_fsb(); |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 88 | /* |
| 89 | * Result is that FSB is incorrect on s3 resume (fixed at 800MHz). |
| 90 | * Some CPU accept this others don't. |
| 91 | */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 92 | if (!s3_resume && setup_sio_gpio(c_bsel)) { |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 93 | printk(BIOS_DEBUG, |
| 94 | "Needs reset to configure CPU BSEL straps\n"); |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 95 | full_reset(); |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 96 | } |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 97 | } |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 98 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 99 | void bootblock_mainboard_early_init(void) |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 100 | { |
| 101 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 102 | } |