Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz |
| 6 | * Copyright (C) 2016 Kyösti Mälkki <kyosti.malkki@gmail.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame^] | 18 | #include <bootblock_common.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 19 | #include <stdint.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 20 | #include <cf9_reset.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 21 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 23 | #include <superio/winbond/common/winbond.h> |
| 24 | #include <superio/winbond/w83627dhg/w83627dhg.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 25 | #include <console/console.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 26 | #include <northbridge/intel/i945/i945.h> |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 27 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 28 | #include <cpu/x86/msr.h> |
| 29 | #include <cpu/intel/speedstep.h> |
| 30 | #include <arch/cpu.h> |
| 31 | |
| 32 | #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) |
| 33 | #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) |
| 34 | |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 35 | /* |
| 36 | * BSEL0 is connected with GPIO32 |
| 37 | * BSEL1 is connected with GPIO33 with inversed logic |
| 38 | * BSEL2 is connected with GPIO55 |
| 39 | */ |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 40 | static int setup_sio_gpio(u8 bsel) |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 41 | { |
| 42 | int need_reset = 0; |
| 43 | u8 reg, old_reg; |
| 44 | |
| 45 | pnp_enter_ext_func_mode(GPIO_DEV); |
| 46 | pnp_set_logical_device(GPIO_DEV); |
| 47 | |
| 48 | reg = 0x9a; |
| 49 | old_reg = pnp_read_config(GPIO_DEV, 0x2c); |
| 50 | pnp_write_config(GPIO_DEV, 0x2c, reg); |
| 51 | need_reset = (reg != old_reg); |
| 52 | |
| 53 | pnp_write_config(GPIO_DEV, 0x30, 0x0e); |
| 54 | pnp_write_config(GPIO_DEV, 0xe0, 0xde); |
| 55 | pnp_write_config(GPIO_DEV, 0xf0, 0xf3); |
| 56 | pnp_write_config(GPIO_DEV, 0xf4, 0x80); |
| 57 | pnp_write_config(GPIO_DEV, 0xf5, 0x80); |
| 58 | |
| 59 | /* Invert GPIO33 */ |
| 60 | pnp_write_config(GPIO_DEV, 0xf2, 0x08); |
| 61 | |
| 62 | reg = (bsel & 3) << 2; |
| 63 | old_reg = pnp_read_config(GPIO_DEV, 0xf1); |
| 64 | pnp_write_config(GPIO_DEV, 0xf1, reg); |
| 65 | need_reset += ((reg & 0xc) != (old_reg & 0xc)); |
| 66 | |
| 67 | reg = (bsel >> 2) << 5; |
| 68 | old_reg = pnp_read_config(GPIO_DEV, 0xe1); |
| 69 | pnp_write_config(GPIO_DEV, 0xe1, reg); |
| 70 | need_reset += ((reg & 0x20) != (old_reg & 0x20)); |
| 71 | |
| 72 | pnp_exit_ext_func_mode(GPIO_DEV); |
| 73 | |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 74 | return need_reset; |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static u8 msr_get_fsb(void) |
| 78 | { |
| 79 | u8 fsbcfg; |
| 80 | msr_t msr; |
| 81 | const u32 eax = cpuid_eax(1); |
| 82 | |
| 83 | /* Netburst */ |
| 84 | if (((eax >> 8) & 0xf) == 0xf) { |
Elyes HAOUAS | f6bbc60 | 2017-11-26 15:34:20 +0100 | [diff] [blame] | 85 | msr = rdmsr(MSR_EBC_FREQUENCY_ID); |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 86 | fsbcfg = (msr.lo >> 16) & 0x7; |
| 87 | } else { /* Intel Core 2 */ |
| 88 | msr = rdmsr(MSR_FSB_FREQ); |
| 89 | fsbcfg = msr.lo & 0x7; |
| 90 | } |
| 91 | |
| 92 | return fsbcfg; |
| 93 | } |
| 94 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 95 | void mainboard_late_rcba_config(void) |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 96 | { |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 97 | /* Enable PCIe Root Port Clock Gate */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 98 | RCBA32(CG) = 0x00000001; |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 99 | } |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 100 | |
| 101 | void mainboard_pre_raminit_config(int s3_resume) |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 102 | { |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 103 | u8 c_bsel = msr_get_fsb(); |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 104 | /* |
| 105 | * Result is that FSB is incorrect on s3 resume (fixed at 800MHz). |
| 106 | * Some CPU accept this others don't. |
| 107 | */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 108 | if (!s3_resume && setup_sio_gpio(c_bsel)) { |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 109 | printk(BIOS_DEBUG, |
| 110 | "Needs reset to configure CPU BSEL straps\n"); |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 111 | full_reset(); |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 112 | } |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 113 | } |
Arthur Heymans | 4231568 | 2017-05-06 00:28:12 +0200 | [diff] [blame] | 114 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame^] | 115 | void bootblock_mainboard_early_init(void) |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 116 | { |
| 117 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Arthur Heymans | 6390e52 | 2016-11-21 17:11:48 +0100 | [diff] [blame] | 118 | } |