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review.coreboot.org / coreboot / b907d321a5d0957f5cbb03d8f9c8d0ff0c23523b / . / src / mainboard / intel / d945gclf / mptable.c
blob: 6edbfe4d29ae3b1ddb14e414979c157976bc6d24 [file] [log] [blame]
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
Uwe Hermann2d2f0c12009-10-28 17:36:11 +0000[diff] [blame]8 * published by the Free Software Foundation; version 2 of the License.
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Uwe Hermann2d2f0c12009-10-28 17:36:11 +0000[diff] [blame]17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]18 */
19
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]20#include <device/device.h>
21#include <device/pci.h>
22#include <console/console.h>
23#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]24#include <arch/ioapic.h>
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]25#include <string.h>
26#include <stdint.h>
27
Stefan Reinauer53b0ea42010-03-22 11:50:52 +0000[diff] [blame]28static void *smp_write_config_table(void *v)
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]29{
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]30 struct mp_config_table *mc;
31 int i;
32 int max_pci_bus, isa_bus;
33
34 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]35
Uwe Hermann55dc2232010-10-25 15:32:07 +0000[diff] [blame]36 mptable_init(mc, "D945GCLF ", LAPIC_ADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]37
38 smp_write_processors(mc);
39
40 max_pci_bus = 5; // XXX read me from bridges.
41
42 /* ISA bus follows */
43 isa_bus = max_pci_bus + 1;
44
45 /* Bus: Bus ID Type */
46 for (i=0; i <= max_pci_bus; i++)
47 smp_write_bus(mc, i, "PCI ");
48
49 smp_write_bus(mc, isa_bus, "ISA ");
50
51 /* I/O APICs: APIC ID Version State Address */
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]52 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]53
54 /* Legacy Interrupts */
55
Patrick Georgic5b87c82010-05-20 15:28:19 +0000[diff] [blame]56 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]57
58 /* Builtin devices on Bus 0 */
59 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
61 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
62 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
68
69 /* Firewire 4:0.0 */
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
71
72 /* Old riser card */
73 // riser slot top 5:8.0
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
75 // riser slot middle 5:9.0
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
77 // riser slot bottom 5:a.0
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
79
80 /* New Riser Card */
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
84
85 /* Onboard Ethernet */
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
87
88 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Tobias Diedrichb907d322010-10-26 22:40:16 +0000[diff] [blame^]89 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
90 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]91
92 /* Compute the checksums */
93 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
94 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
95
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]96 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]97
98 return smp_next_mpe_entry(mc);
99}
100
101unsigned long write_smp_table(unsigned long addr)
102{
103 void *v;
104 v = smp_write_floating_table(addr);
105 return (unsigned long)smp_write_config_table(v);
106}