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review.coreboot.org / coreboot / c02b4fc9db3c3c1e263027382697b566127f66bb / . / src / mainboard / intel / d945gclf / mptable.c
blob: db5ee12b01233fa392c4e7ef04e8056e0071464b [file] [log] [blame]
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
Uwe Hermann2d2f0c12009-10-28 17:36:11 +0000[diff] [blame]8 * published by the Free Software Foundation; version 2 of the License.
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Uwe Hermann2d2f0c12009-10-28 17:36:11 +0000[diff] [blame]17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]18 */
19
20
21#include <device/device.h>
22#include <device/pci.h>
23#include <console/console.h>
24#include <arch/smp/mpspec.h>
25#include <string.h>
26#include <stdint.h>
27
28void *smp_write_config_table(void *v)
29{
30 static const char sig[4] = "PCMP";
31 static const char oem[8] = "COREBOOT";
32 static const char productid[12] = "D945GCLF ";
33 struct mp_config_table *mc;
34 int i;
35 int max_pci_bus, isa_bus;
36
37 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
38 memset(mc, 0, sizeof(*mc));
39
40 memcpy(mc->mpc_signature, sig, sizeof(sig));
41 mc->mpc_length = sizeof(*mc); /* initially just the header */
42 mc->mpc_spec = 0x04;
43 mc->mpc_checksum = 0; /* not yet computed */
44 memcpy(mc->mpc_oem, oem, sizeof(oem));
45 memcpy(mc->mpc_productid, productid, sizeof(productid));
46 mc->mpc_oemptr = 0;
47 mc->mpc_oemsize = 0;
48 mc->mpc_entry_count = 0; /* No entries yet... */
49 mc->mpc_lapic = LAPIC_ADDR;
50 mc->mpe_length = 0;
51 mc->mpe_checksum = 0;
52 mc->reserved = 0;
53
54 smp_write_processors(mc);
55
56 max_pci_bus = 5; // XXX read me from bridges.
57
58 /* ISA bus follows */
59 isa_bus = max_pci_bus + 1;
60
61 /* Bus: Bus ID Type */
62 for (i=0; i <= max_pci_bus; i++)
63 smp_write_bus(mc, i, "PCI ");
64
65 smp_write_bus(mc, isa_bus, "ISA ");
66
67 /* I/O APICs: APIC ID Version State Address */
68 smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
69
70 /* Legacy Interrupts */
71
72 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
73 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
75 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
86
87 /* Builtin devices on Bus 0 */
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
97
98 /* Firewire 4:0.0 */
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
100
101 /* Old riser card */
102 // riser slot top 5:8.0
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
104 // riser slot middle 5:9.0
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
106 // riser slot bottom 5:a.0
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
108
109 /* New Riser Card */
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
113
114 /* Onboard Ethernet */
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
116
117 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
118 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
119 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
120
121 /* Compute the checksums */
122 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
123 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
124
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame^]125 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
Stefan Reinauer1a08f582009-10-28 16:52:48 +0000[diff] [blame]126
127 return smp_next_mpe_entry(mc);
128}
129
130unsigned long write_smp_table(unsigned long addr)
131{
132 void *v;
133 v = smp_write_floating_table(addr);
134 return (unsigned long)smp_write_config_table(v);
135}