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Angel Ponsf94ac9a2020-04-05 15:46:48 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Duncan Lauriec88c54c2014-04-30 16:36:13 -07003
4#include <console/console.h>
5#include <device/device.h>
6#include <device/pci.h>
7#include <device/pci_ids.h>
8#include <device/pci_ops.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02009#include <device/mmio.h>
Duncan Lauriec88c54c2014-04-30 16:36:13 -070010#include <soc/intel/common/hda_verb.h>
Julius Werner4ee4bd52014-10-20 13:46:39 -070011#include <soc/ramstage.h>
Matt DeVillierf8960a62016-11-16 23:37:43 -060012#include <soc/igd.h>
Duncan Lauriec88c54c2014-04-30 16:36:13 -070013
14static const u32 minihd_verb_table[] = {
15 /* coreboot specific header */
Matt DeVilliereafa2032019-12-19 19:39:25 -060016 0x80862808, // Codec Vendor / Device ID: Intel Broadwell Mini-HD
17 0x80860101, // Subsystem ID
Duncan Lauriec88c54c2014-04-30 16:36:13 -070018 0x00000004, // Number of jacks
19
20 /* Enable 3rd Pin and Converter Widget */
21 0x00878101,
22
23 /* Pin Widget 5 - PORT B */
24 0x00571C10,
25 0x00571D00,
26 0x00571E56,
27 0x00571F18,
28
29 /* Pin Widget 6 - PORT C */
30 0x00671C20,
31 0x00671D00,
32 0x00671E56,
33 0x00671F18,
34
35 /* Pin Widget 7 - PORT D */
36 0x00771C30,
37 0x00771D00,
38 0x00771E56,
39 0x00771F18,
40
41 /* Disable 3rd Pin and Converter Widget */
42 0x00878100,
43
44 /* Dummy entries to fill out the table */
45 0x00878100,
46 0x00878100,
47};
48
49static void minihd_init(struct device *dev)
50{
51 struct resource *res;
Jacob Garberea61c0e2019-07-22 12:53:27 -060052 u8 *base;
53 u32 reg32;
Duncan Lauriec88c54c2014-04-30 16:36:13 -070054 int codec_mask, i;
55
56 /* Find base address */
57 res = find_resource(dev, PCI_BASE_ADDRESS_0);
58 if (!res)
59 return;
60
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080061 base = res2mmio(res, 0, 0);
62 printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
Duncan Lauriec88c54c2014-04-30 16:36:13 -070063
64 /* Set Bus Master */
Elyes HAOUASb887adf2020-04-29 10:42:34 +020065 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
Duncan Lauriec88c54c2014-04-30 16:36:13 -070066
67 /* Mini-HD configuration */
68 reg32 = read32(base + 0x100c);
69 reg32 &= 0xfffc0000;
70 reg32 |= 0x4;
71 write32(base + 0x100c, reg32);
72
73 reg32 = read32(base + 0x1010);
74 reg32 &= 0xfffc0000;
75 reg32 |= 0x4b;
76 write32(base + 0x1010, reg32);
77
78 /* Init the codec and write the verb table */
79 codec_mask = hda_codec_detect(base);
80
81 if (codec_mask) {
82 for (i = 3; i >= 0; i--) {
83 if (codec_mask & (1 << i))
84 hda_codec_init(base, i,
85 sizeof(minihd_verb_table),
86 minihd_verb_table);
87 }
88 }
Matt DeVillierf8960a62016-11-16 23:37:43 -060089
90 /* Set EM4/EM5 registers */
91 write32(base + 0x0100c, igd_get_reg_em4());
92 write32(base + 0x01010, igd_get_reg_em5());
Duncan Lauriec88c54c2014-04-30 16:36:13 -070093}
94
95static struct device_operations minihd_ops = {
96 .read_resources = &pci_dev_read_resources,
97 .set_resources = &pci_dev_set_resources,
98 .enable_resources = &pci_dev_enable_resources,
99 .init = &minihd_init,
100 .ops_pci = &broadwell_pci_ops,
101};
102
103static const unsigned short pci_device_ids[] = {
104 0x0a0c, /* Haswell */
105 0x160c, /* Broadwell */
106 0
107};
108
109static const struct pci_driver minihd_driver __pci_driver = {
110 .ops = &minihd_ops,
111 .vendor = PCI_VENDOR_ID_INTEL,
112 .devices = pci_device_ids,
113};