blob: 0acf98bbffc0a2ae74de9050f6b00dcf37a25c9b [file] [log] [blame]
James Yebe6fd4c2017-07-22 19:19:42 +10001chip northbridge/intel/sandybridge
2 # IGD Displays
Nico Huberb0b25c82020-03-21 20:35:12 +01003 register "gfx" = "GMA_STATIC_DISPLAYS(1)"
James Yebe6fd4c2017-07-22 19:19:42 +10004
5 register "gpu_dp_d_hotplug" = "0x04"
6
7 # Enable Panel as LVDS and configure power delays
Angel Ponsdc0c0812020-09-02 19:17:30 +02008 register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
James Yebe6fd4c2017-07-22 19:19:42 +10009 register "gpu_panel_power_cycle_delay" = "4"
10 register "gpu_panel_power_up_delay" = "100"
11 register "gpu_panel_power_down_delay" = "100"
12 register "gpu_panel_power_backlight_on_delay" = "3000"
13 register "gpu_panel_power_backlight_off_delay" = "2000"
James Yebe6fd4c2017-07-22 19:19:42 +100014 register "gpu_cpu_backlight" = "0x1155"
15 register "gpu_pch_backlight" = "0x11551155"
16
Angel Ponsbceea672021-05-17 10:58:36 +020017 device domain 0 on
James Yebe6fd4c2017-07-22 19:19:42 +100018 subsystemid 0x17aa 0x21fe inherit
19
Arthur Heymansb5df65a2022-11-12 14:51:49 +010020 device ref host_bridge on end # Host bridge
21 device ref peg10 off end # PCIe Bridge for discrete graphics
22 device ref igd on end # Internal graphics VGA controller
23 device ref dev4 off end # Signal processing controller
James Yebe6fd4c2017-07-22 19:19:42 +100024
25 chip southbridge/intel/bd82x6x
26 # GPI routing
27 register "alt_gp_smi_en" = "0x0000"
28 register "gpi6_routing" = "2"
29 register "gpi13_routing" = "2"
30
James Yeef2e86e2019-02-12 22:17:52 +110031 # Enable SATA ports 0 (2.5 inch) and 1 (mSATA)
32 register "sata_port_map" = "0x3"
James Yebe6fd4c2017-07-22 19:19:42 +100033 # Set max SATA speed to 6.0 Gb/s
34 register "sata_interface_speed_support" = "0x3"
35
36 register "gen1_dec" = "0x007c1611"
37 register "gen2_dec" = "0x00040069"
38 register "gen3_dec" = "0x000c0701"
39 register "gen4_dec" = "0x000c06a1"
40
41 register "xhci_switchable_ports" = "0xf"
42 register "superspeed_capable_ports" = "0xf"
43 register "xhci_overcurrent_mapping" = "0x00000c03"
44
45 # Enable zero-based linear PCIe root port functions
Angel Ponsaf4bd562021-12-28 13:05:56 +010046 register "pcie_port_coalesce" = "true"
James Yebe6fd4c2017-07-22 19:19:42 +100047
48 register "spi_uvscc" = "0x2005"
49 register "spi_lvscc" = "0x2005"
50
Arthur Heymansb5df65a2022-11-12 14:51:49 +010051 device ref xhci on end # USB 3.0 Controller
52 device ref mei1 on end # Management Engine Interface 1
53 device ref mei2 off end # Management Engine Interface 2
54 device ref me_ide_r off end # Management Engine IDE-R
55 device ref me_kt off end # Management Engine KT
56 device ref gbe off end # Intel Gigabit Ethernet
57 device ref ehci2 on end # USB2 EHCI #2
58 device ref hda on end # High Definition Audio Audio controller
59 device ref pcie_rp1 on end # PCIe Port #1
60 device ref pcie_rp2 on end # PCIe Port #2 (WLAN card)
61 device ref pcie_rp3 on end # PCIe Port #3 (Card Reader)
62 device ref pcie_rp4 off end # PCIe Port #4
63 device ref pcie_rp5 off end # PCIe Port #5
64 device ref pcie_rp6 on end # PCIe Port #6 (Ethernet controller)
65 device ref pcie_rp7 off end # PCIe Port #7
66 device ref pcie_rp8 off end # PCIe Port #8
67 device ref ehci1 on end # USB2 EHCI #1
68 device ref pci_bridge off end # PCI bridge
69 device ref lpc on # LPC bridge PCI-LPC bridge
James Yebe6fd4c2017-07-22 19:19:42 +100070 chip drivers/pc80/tpm
71 device pnp 0c31.0 on end
72 end
73
74 chip ec/lenovo/h8
James Yea6450d72019-01-19 18:25:04 +110075 device pnp ff.1 on # dummy
James Yebe6fd4c2017-07-22 19:19:42 +100076 io 0x60 = 0x62
77 io 0x62 = 0x66
78 io 0x64 = 0x1600
79 io 0x66 = 0x1604
80 end
81
82 register "config0" = "0xa6"
83 register "config1" = "0x04"
84 register "config2" = "0xa0"
85 register "config3" = "0x62"
86
87 register "has_keyboard_backlight" = "0"
88
89 register "beepmask0" = "0x00"
90 register "beepmask1" = "0x87"
91 register "has_power_management_beeps" = "0"
92
93 register "event0_enable" = "0xff"
94 register "event1_enable" = "0xff"
95 register "event2_enable" = "0xff"
96 register "event3_enable" = "0xff"
97 register "event4_enable" = "0xff"
98 register "event5_enable" = "0xff"
99 register "event6_enable" = "0xff"
100 register "event7_enable" = "0xff"
101 register "event8_enable" = "0xff"
102 register "event9_enable" = "0xff"
103 register "eventa_enable" = "0xff"
104 register "eventb_enable" = "0xff"
105 register "eventc_enable" = "0xff"
106 register "eventd_enable" = "0xff"
107 register "evente_enable" = "0xff"
108 register "eventf_enable" = "0xff"
109 end
110 end
Arthur Heymansb5df65a2022-11-12 14:51:49 +0100111 device ref sata1 on end # SATA Controller 1
112 device ref smbus on # SMBus
James Yebe6fd4c2017-07-22 19:19:42 +1000113 # eeprom, 8 virtual devices, same chip
114 chip drivers/i2c/at24rf08c
115 device i2c 54 on end
116 device i2c 55 on end
117 device i2c 56 on end
118 device i2c 57 on end
119 device i2c 5c on end
120 device i2c 5d on end
121 device i2c 5e on end
122 device i2c 5f on end
123 end
124 end
Arthur Heymansb5df65a2022-11-12 14:51:49 +0100125 device ref sata2 off end # SATA Controller 2
126 device ref thermal off end # Thermal
James Yebe6fd4c2017-07-22 19:19:42 +1000127 end
128 end
129end