mb/lenovo: add Lenovo ThinkPad X131e (Intel)

The Intel version of ThinkPad X131e can ship with Sandy Bridge or
Ivy Bridge processors.  The mainboard uses 8MiB+4MiB flash chips, with
the 8MiB chip containing the IFD and ME, and the 4MiB chip containing
the BIOS.  The flash chips can be accessed with an external programmer.

This port was primarily created using autoport, with some parts adapted
from lenovo/x230 and google/stout.

Tested and working:
 - Machine type 3367AH5 / Intel Celeron 887 (Sandy Bridge)
 - Boots Debian GNU/Linux 9.2 (Linux 4.9.51) via SeaBIOS
 - Boot from internal SATA and USB
 - Native RAM init
 - Native VGA init
 - libgfxinit
 - VGA and HDMI display output
 - Keyboard, trackpoint, touchpad
 - Audio (speaker, headphones)
 - Ethernet (Realtek)
 - Display backlight
 - USB 3.0 ports
 - "Always on" USB port (EHCI debug)
 - SD card reader
 - Webcam
 - Fan and temperature sensors
 - ACPI S3 (Sleep)
 - CMOS
 - TPM

Not tested:
 - WLAN/Bluetooth (Broadcom)
 - WWAN/mSATA (no card)
 - Other operating systems

Not working or not implemented:
 - Fn keys
 - ACPI S4 (Hibernation) "Image mismatch: memory size"

Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/20694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb
new file mode 100644
index 0000000..ccdff7c
--- /dev/null
+++ b/src/mainboard/lenovo/x131e/devicetree.cb
@@ -0,0 +1,160 @@
+chip northbridge/intel/sandybridge
+	# IGD Displays
+	register "gfx.ndid" = "3"
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+
+	register "gpu_dp_d_hotplug" = "0x04"
+
+	# Enable Panel as LVDS and configure power delays
+	register "gpu_panel_port_select" = "0"
+	register "gpu_panel_power_cycle_delay" = "4"
+	register "gpu_panel_power_up_delay" = "100"
+	register "gpu_panel_power_down_delay" = "100"
+	register "gpu_panel_power_backlight_on_delay" = "3000"
+	register "gpu_panel_power_backlight_off_delay" = "2000"
+	register "gfx.use_spread_spectrum_clock" = "1"
+	register "gfx.link_frequency_270_mhz" = "1"
+	register "gpu_cpu_backlight" = "0x1155"
+	register "gpu_pch_backlight" = "0x11551155"
+
+	device cpu_cluster 0x0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0x0 on end
+		end
+		chip cpu/intel/model_206ax
+			# Magic APIC ID to locate this chip
+			device lapic 0xacac off end
+
+			register "c1_acpower" = "1"
+			register "c2_acpower" = "3"
+			register "c3_acpower" = "5"
+
+			register "c1_battery" = "1"
+			register "c2_battery" = "3"
+			register "c3_battery" = "5"
+		end
+	end
+
+	register "pci_mmio_size" = "1024"
+
+	device domain 0x0 on
+		subsystemid 0x17aa 0x21fe inherit
+
+		device pci 00.0 on end # Host bridge
+		device pci 01.0 off end # PCIe Bridge for discrete graphics
+		device pci 02.0 on end # Internal graphics VGA controller
+		device pci 04.0 off end # Signal processing controller
+
+		chip southbridge/intel/bd82x6x
+			# GPI routing
+			register "alt_gp_smi_en" = "0x0000"
+			register "gpi6_routing" = "2"
+			register "gpi13_routing" = "2"
+
+			# Enable SATA ports
+			register "sata_port_map" = "0x1"
+			# Set max SATA speed to 6.0 Gb/s
+			register "sata_interface_speed_support" = "0x3"
+
+			register "gen1_dec" = "0x007c1611"
+			register "gen2_dec" = "0x00040069"
+			register "gen3_dec" = "0x000c0701"
+			register "gen4_dec" = "0x000c06a1"
+
+			register "xhci_switchable_ports" = "0xf"
+			register "superspeed_capable_ports" = "0xf"
+			register "xhci_overcurrent_mapping" = "0x00000c03"
+
+			# Enable zero-based linear PCIe root port functions
+			register "pcie_port_coalesce" = "1"
+			register "c2_latency" = "0x0065"
+			register "p_cnt_throttling_supported" = "1"
+
+			register "spi_uvscc" = "0x2005"
+			register "spi_lvscc" = "0x2005"
+
+			device pci 14.0 on end # USB 3.0 Controller
+			device pci 16.0 off end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2
+			device pci 1b.0 on end # High Definition Audio Audio controller
+			device pci 1c.0 on end # PCIe Port #1
+			device pci 1c.1 on end # PCIe Port #2 (WLAN card)
+			device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 on end # PCIe Port #6 (Ethernet controller)
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+				chip ec/lenovo/pmh7
+					register "backlight_enable" = "0x01"
+					register "dock_event_enable" = "0x00"
+					device pnp ff.1 on end # dummy
+				end
+
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
+
+				chip ec/lenovo/h8
+					device pnp ff.2 on # dummy
+						io 0x60 = 0x62
+						io 0x62 = 0x66
+						io 0x64 = 0x1600
+						io 0x66 = 0x1604
+					end
+
+					register "config0" = "0xa6"
+					register "config1" = "0x04"
+					register "config2" = "0xa0"
+					register "config3" = "0x62"
+
+					register "has_keyboard_backlight" = "0"
+
+					register "beepmask0" = "0x00"
+					register "beepmask1" = "0x87"
+					register "has_power_management_beeps" = "0"
+
+					register "event0_enable" = "0xff"
+					register "event1_enable" = "0xff"
+					register "event2_enable" = "0xff"
+					register "event3_enable" = "0xff"
+					register "event4_enable" = "0xff"
+					register "event5_enable" = "0xff"
+					register "event6_enable" = "0xff"
+					register "event7_enable" = "0xff"
+					register "event8_enable" = "0xff"
+					register "event9_enable" = "0xff"
+					register "eventa_enable" = "0xff"
+					register "eventb_enable" = "0xff"
+					register "eventc_enable" = "0xff"
+					register "eventd_enable" = "0xff"
+					register "evente_enable" = "0xff"
+					register "eventf_enable" = "0xff"
+				end
+			end
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on # SMBus
+				# eeprom, 8 virtual devices, same chip
+				chip drivers/i2c/at24rf08c
+					device i2c 54 on end
+					device i2c 55 on end
+					device i2c 56 on end
+					device i2c 57 on end
+					device i2c 5c on end
+					device i2c 5d on end
+					device i2c 5e on end
+					device i2c 5f on end
+				end
+			end
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end