blob: 739d01db1c85123cc42825b159b40db1b93266ad [file] [log] [blame]
Nicolas Reinecke29d358e2015-01-31 19:20:50 +01001chip northbridge/intel/sandybridge
Nico Huberb0b25c82020-03-21 20:35:12 +01002 register "gfx" = "GMA_STATIC_DISPLAYS(1)"
Nicolas Reinecke29d358e2015-01-31 19:20:50 +01003
4 # Enable DisplayPort Hotplug with 6ms pulse
5 register "gpu_dp_d_hotplug" = "0x06"
6
7 # Enable Panel as LVDS and configure power delays
Angel Ponsdc0c0812020-09-02 19:17:30 +02008 register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
Nicolas Reinecke29d358e2015-01-31 19:20:50 +01009 register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
10 register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
11 register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
12 register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
13 register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010014 register "gpu_cpu_backlight" = "0x1155"
15 register "gpu_pch_backlight" = "0x11551155"
16
17 device cpu_cluster 0 on
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010018 chip cpu/intel/model_206ax
19 # Magic APIC ID to locate this chip
Angel Ponsc56c7232021-05-17 11:03:55 +020020 device lapic 0 on end
Arthur Heymansb3f23232019-01-21 17:48:55 +010021 device lapic 0xacac off end
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010022
Angel Pons6f56a232021-01-04 17:02:23 +010023 register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1)
24 register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3)
25 register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7)
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010026 end
27 end
28
29 device domain 0 on
Peter Lemenkovb8b97862019-11-27 23:04:49 +010030 subsystemid 0x17aa 0x21fb inherit
31
32 device pci 00.0 on end # host bridge
Patrick Rudolph830fdc72016-04-21 07:15:14 +020033 device pci 01.0 on end # PCIe Bridge for discrete graphics
Peter Lemenkovb8b97862019-11-27 23:04:49 +010034 device pci 02.0 on end # Integrated Graphics Controller
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010035
36 chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
37 # GPI routing
38 # 0 No effect (default)
39 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
40 # 2 SCI (if corresponding GPIO_EN bit is also set)
41 register "alt_gp_smi_en" = "0x0000"
42 register "gpi1_routing" = "2"
43 register "gpi13_routing" = "2"
44
45 # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock)
46 register "sata_port_map" = "0x17"
47 # Set max SATA speed to 6.0 Gb/s
48 register "sata_interface_speed_support" = "0x3"
49
50 register "gen1_dec" = "0x7c1601"
51 register "gen2_dec" = "0x0c15e1"
52 register "gen4_dec" = "0x0c06a1"
53
54 register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
Bill XIE012ef772018-11-29 20:37:35 +080055 # Wire port 4 (wwan usb) to ehci for it lacks superspeed components
56 register "xhci_switchable_ports" = "0x7"
Nicolas Reineckebcff3bd2015-03-31 01:40:46 +020057 register "superspeed_capable_ports" = "0xf"
58 register "xhci_overcurrent_mapping" = "0x4000201"
59
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010060 # Enable zero-based linear PCIe root port functions
Angel Ponsaf4bd562021-12-28 13:05:56 +010061 register "pcie_port_coalesce" = "true"
Bill XIE012ef772018-11-29 20:37:35 +080062 register "docking_supported" = "1"
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010063
Patrick Rudolphc670a412017-04-28 17:28:32 +020064 register "spi_uvscc" = "0x2005"
65 register "spi_lvscc" = "0x2005"
66
Peter Lemenkovb8b97862019-11-27 23:04:49 +010067 device pci 14.0 on end # USB 3.0 Controller
Evgeny Zinovievb5d402e2020-06-16 04:41:48 +030068 device pci 16.0 on end # Management Engine Interface 1
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010069 device pci 16.1 off end # Management Engine Interface 2
70 device pci 16.2 off end # Management Engine IDE-R
71 device pci 16.3 off end # Management Engine KT
72 device pci 19.0 on
73 subsystemid 0x17aa 0x21f3
74 end # Intel Gigabit Ethernet
Peter Lemenkovb8b97862019-11-27 23:04:49 +010075 device pci 1a.0 on end # USB Enhanced Host Controller #2
76 device pci 1b.0 on end # High Definition Audio Controller
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010077 device pci 1c.0 off end # PCIe Port #1
Peter Lemenkovb8b97862019-11-27 23:04:49 +010078 device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010079 device pci 1c.2 on
Patrick Rudolph05216322019-04-12 16:14:27 +020080 smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010081 end # PCIe Port #3 ExpressCard
82 device pci 1c.3 off end # PCIe Port #4
83 device pci 1c.4 off end # PCIe Port #5
84 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe)
85 device pci 1c.6 off end # PCIe Port #7
86 device pci 1c.7 off end # PCIe Port #8
Peter Lemenkovb8b97862019-11-27 23:04:49 +010087 device pci 1d.0 on end # USB Enhanced Host Controller #1
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010088 device pci 1e.0 off end # PCI bridge
89 device pci 1f.0 on
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010090 chip ec/lenovo/pmh7
Peter Lemenkovb8b97862019-11-27 23:04:49 +010091 device pnp ff.1 on end # dummy
Nicolas Reinecke29d358e2015-01-31 19:20:50 +010092 register "backlight_enable" = "0x01"
93 register "dock_event_enable" = "0x01"
94 end
95
Philipp Deppenwiese3d02b9c2015-06-03 23:09:36 +020096 chip drivers/pc80/tpm
97 device pnp 0c31.0 on end
98 end
99
Nicolas Reinecke29d358e2015-01-31 19:20:50 +0100100 chip ec/lenovo/h8
101 device pnp ff.2 on # dummy
102 io 0x60 = 0x62
103 io 0x62 = 0x66
104 io 0x64 = 0x1600
105 io 0x66 = 0x1604
106 end
107
108 register "config0" = "0xa7"
109 register "config1" = "0x05"
110 register "config2" = "0xa0"
111 register "config3" = "0xe2"
112
113 register "has_keyboard_backlight" = "1"
114
115 register "beepmask0" = "0x00"
116 register "beepmask1" = "0x86"
117 register "has_power_management_beeps" = "0"
118 register "event2_enable" = "0xff"
119 register "event3_enable" = "0xff"
120 register "event4_enable" = "0xd0"
121 register "event5_enable" = "0x3c"
122 register "event6_enable" = "0x00"
123 register "event7_enable" = "0x01"
124 register "event8_enable" = "0x7b"
125 register "event9_enable" = "0xff"
126 register "eventa_enable" = "0x00"
127 register "eventb_enable" = "0x00"
128 register "eventc_enable" = "0xff"
129 register "eventd_enable" = "0xff"
130 register "evente_enable" = "0x0d"
Nicolas Reinecke29d358e2015-01-31 19:20:50 +0100131 end
132 end # LPC Controller
Peter Lemenkovb8b97862019-11-27 23:04:49 +0100133 device pci 1f.2 on end # 6 port SATA AHCI Controller
Nicolas Reinecke29d358e2015-01-31 19:20:50 +0100134 device pci 1f.3 on
Nicolas Reinecke29d358e2015-01-31 19:20:50 +0100135 # eeprom, 8 virtual devices, same chip
136 chip drivers/i2c/at24rf08c
137 device i2c 54 on end
138 device i2c 55 on end
139 device i2c 56 on end
140 device i2c 57 on end
141 device i2c 5c on end
142 device i2c 5d on end
143 device i2c 5e on end
144 device i2c 5f on end
145 end
146 end # SMBus Controller
147 device pci 1f.5 off end # SATA Controller 2
Peter Lemenkovb8b97862019-11-27 23:04:49 +0100148 device pci 1f.6 on end # Thermal
Nicolas Reinecke29d358e2015-01-31 19:20:50 +0100149 end
150 end
151end