blob: cec5070a1046d3e7af99e50f254e9ae46d062ac2 [file] [log] [blame]
Angel Pons5f1bf2f2020-04-03 01:21:16 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Felix Held972d9f22022-02-23 16:32:20 +01002
Arthur Heymansfa5d0f82019-11-12 19:11:50 +01003#include <bootblock_common.h>
Keith Huib4a89372023-07-21 19:26:13 -04004#include <device/pnp_type.h>
Vlado Cibic2bf6a302019-06-09 06:53:50 +00005#include <southbridge/intel/bd82x6x/pch.h>
6
7#include <superio/nuvoton/common/nuvoton.h>
8#include <superio/nuvoton/nct6779d/nct6779d.h>
9
10#include <option.h>
11
Vlado Cibic2bf6a302019-06-09 06:53:50 +000012#include <northbridge/intel/sandybridge/raminit.h>
13#include <northbridge/intel/sandybridge/pei_data.h>
14
Vlado Cibic2bf6a302019-06-09 06:53:50 +000015#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2)
16
Vlado Cibic2bf6a302019-06-09 06:53:50 +000017const struct southbridge_usb_port mainboard_usb_ports[] = {
18 /* {enable, current, oc_pin} */
19 { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */
20 { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */
21 { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */
22 { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */
23 { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */
24 { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */
25 { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */
26 { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */
27 { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */
28 { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
29 { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */
30 { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */
Elyes HAOUASb7da27c2020-01-11 19:21:07 +010031 { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */
32 { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */
Vlado Cibic2bf6a302019-06-09 06:53:50 +000033};
34
Arthur Heymansfa5d0f82019-11-12 19:11:50 +010035void bootblock_mainboard_early_init(void)
Vlado Cibic2bf6a302019-06-09 06:53:50 +000036{
Vlado Cibic2bf6a302019-06-09 06:53:50 +000037 nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
38}
39
Vlado Cibic2bf6a302019-06-09 06:53:50 +000040void mainboard_fill_pei_data(struct pei_data *pei_data)
41{
42 /*
43 * USB3 mode:
44 * 0 = Disable: work always as USB 2.0(ehci)
45 * 1 = Enable: work always as USB 3.0(xhci)
46 * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver
47 * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
48 * and reboots, it will keep the USB3.0 speed
49 */
Keith Hui7039edd2023-07-21 10:12:05 -040050 pei_data->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3;
Vlado Cibic2bf6a302019-06-09 06:53:50 +000051 /* Load USB3 pre-OS xHCI driver */
Keith Hui7039edd2023-07-21 10:12:05 -040052 pei_data->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1;
Vlado Cibic2bf6a302019-06-09 06:53:50 +000053 /* Use USB3 xHCI streams */
Keith Hui7039edd2023-07-21 10:12:05 -040054 pei_data->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1;
Vlado Cibic2bf6a302019-06-09 06:53:50 +000055}