Angel Pons | 5f1bf2f | 2020-04-03 01:21:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Felix Held | 972d9f2 | 2022-02-23 16:32:20 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 3 | #include <bootblock_common.h> |
Keith Hui | b4a8937 | 2023-07-21 19:26:13 -0400 | [diff] [blame^] | 4 | #include <device/pnp_type.h> |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 5 | #include <southbridge/intel/bd82x6x/pch.h> |
| 6 | |
| 7 | #include <superio/nuvoton/common/nuvoton.h> |
| 8 | #include <superio/nuvoton/nct6779d/nct6779d.h> |
| 9 | |
| 10 | #include <option.h> |
| 11 | |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 12 | #include <northbridge/intel/sandybridge/raminit.h> |
| 13 | #include <northbridge/intel/sandybridge/pei_data.h> |
| 14 | |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 15 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) |
| 16 | |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 17 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 18 | /* {enable, current, oc_pin} */ |
| 19 | { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ |
| 20 | { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ |
| 21 | { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ |
| 22 | { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ |
| 23 | { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ |
| 24 | { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ |
| 25 | { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ |
| 26 | { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ |
| 27 | { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ |
| 28 | { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ |
| 29 | { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ |
| 30 | { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ |
Elyes HAOUAS | b7da27c | 2020-01-11 19:21:07 +0100 | [diff] [blame] | 31 | { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ |
| 32 | { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 33 | }; |
| 34 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 35 | void bootblock_mainboard_early_init(void) |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 36 | { |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 37 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 38 | } |
| 39 | |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 40 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
| 41 | { |
| 42 | /* |
| 43 | * USB3 mode: |
| 44 | * 0 = Disable: work always as USB 2.0(ehci) |
| 45 | * 1 = Enable: work always as USB 3.0(xhci) |
| 46 | * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver |
| 47 | * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver |
| 48 | * and reboots, it will keep the USB3.0 speed |
| 49 | */ |
Keith Hui | 7039edd | 2023-07-21 10:12:05 -0400 | [diff] [blame] | 50 | pei_data->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3; |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 51 | /* Load USB3 pre-OS xHCI driver */ |
Keith Hui | 7039edd | 2023-07-21 10:12:05 -0400 | [diff] [blame] | 52 | pei_data->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1; |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 53 | /* Use USB3 xHCI streams */ |
Keith Hui | 7039edd | 2023-07-21 10:12:05 -0400 | [diff] [blame] | 54 | pei_data->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1; |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 55 | } |