Arthur Heymans | 2a4aada | 2017-04-12 13:53:08 +0200 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | # Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> |
| 6 | # |
| 7 | # This program is free software; you can redistribute it and/or modify |
| 8 | # it under the terms of the GNU General Public License as published by |
| 9 | # the Free Software Foundation; either version 2 of the License, or |
| 10 | # (at your option) any later version. |
| 11 | # |
| 12 | # This program is distributed in the hope that it will be useful, |
| 13 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | # GNU General Public License for more details. |
| 16 | # |
| 17 | |
| 18 | chip northbridge/intel/x4x # Northbridge |
| 19 | device cpu_cluster 0 on # APIC cluster |
| 20 | chip cpu/intel/socket_LGA775 |
| 21 | device lapic 0 on end |
| 22 | end |
| 23 | chip cpu/intel/model_1067x # CPU |
| 24 | device lapic 0xACAC off end |
| 25 | end |
| 26 | end |
| 27 | device domain 0 on # PCI domain |
| 28 | device pci 0.0 on end # Host Bridge |
| 29 | device pci 2.0 on end # Integrated graphics controller |
| 30 | device pci 2.1 on end # Integrated graphics controller 2 |
| 31 | device pci 3.0 off end # ME |
| 32 | device pci 3.1 off end # ME |
| 33 | chip southbridge/intel/i82801jx # Southbridge |
| 34 | register "gpe0_en" = "0x40" |
| 35 | |
| 36 | # Set AHCI mode. |
| 37 | register "sata_port_map" = "0x1f" |
| 38 | register "sata_clock_request" = "0" |
| 39 | register "sata_traffic_monitor" = "0" |
| 40 | |
| 41 | # Enable PCIe ports 0,2,3 as slots. |
| 42 | register "pcie_slot_implemented" = "0xb" |
| 43 | |
| 44 | device pci 19.0 on end # GBE |
| 45 | device pci 1a.0 on end # USB |
| 46 | device pci 1a.1 on end # USB |
| 47 | device pci 1a.2 on end # USB |
| 48 | device pci 1a.7 on end # USB |
| 49 | device pci 1b.0 on end # Audio |
| 50 | device pci 1c.0 on end # PCIe 1 |
| 51 | device pci 1c.1 off end # PCIe 2 |
| 52 | device pci 1c.2 on end # PCIe 3 |
| 53 | device pci 1c.3 on end # PCIe 4 |
| 54 | device pci 1c.4 off end # PCIe 5 |
| 55 | device pci 1c.5 off end # PCIe 6 |
| 56 | device pci 1d.0 on end # USB |
| 57 | device pci 1d.1 on end # USB |
| 58 | device pci 1d.2 on end # USB |
| 59 | device pci 1d.7 on end # USB |
| 60 | device pci 1e.0 on end # PCI bridge |
| 61 | device pci 1f.0 on # ISA bridge |
| 62 | chip superio/winbond/w83627dhg # Super I/O |
| 63 | device pnp 2e.0 on # Floppy |
| 64 | # GLOBAL |
| 65 | io 0x60 = 0x3f0 |
| 66 | irq 0x70 = 6 |
| 67 | drq 0x74 = 2 |
| 68 | end |
| 69 | device pnp 2e.1 on # Parallel port |
| 70 | io 0x60 = 0x378 |
| 71 | irq 0x70 = 5 |
| 72 | drq 0x74 = 4 |
| 73 | end |
| 74 | device pnp 2e.2 on # COM 1 |
| 75 | io 0x60 = 0x3f8 |
| 76 | irq 0x70 = 4 |
| 77 | end |
| 78 | device pnp 2e.3 off end # COM 2 |
| 79 | device pnp 2e.5 on # Keyboard |
| 80 | io 0x60 = 0x60 |
| 81 | irq 0x70 = 1 |
| 82 | io 0x62 = 0x64 |
| 83 | irq 0xf0 = 0x85 |
| 84 | end |
| 85 | device pnp 2e.6 off end # SPI |
Arthur Heymans | b474445 | 2017-09-21 18:57:19 +0200 | [diff] [blame^] | 86 | device pnp 2e.7 on end # GPIO 6 |
Arthur Heymans | 2a4aada | 2017-04-12 13:53:08 +0200 | [diff] [blame] | 87 | device pnp 2e.8 off end # WDTO# PLED |
Arthur Heymans | b474445 | 2017-09-21 18:57:19 +0200 | [diff] [blame^] | 88 | device pnp 2e.9 off end # GPIO 2 |
| 89 | device pnp 2e.109 on # GPIO 3 |
| 90 | irq 0xf0 = 0xfc |
| 91 | end |
| 92 | device pnp 2e.209 off end # GPIO 4 |
| 93 | device pnp 2e.309 on # GPIO 5 |
| 94 | irq 0xe0 = 0xde |
| 95 | irq 0xe1 = 0x01 |
Arthur Heymans | 2a4aada | 2017-04-12 13:53:08 +0200 | [diff] [blame] | 96 | end |
| 97 | device pnp 2e.a on # ACPI |
| 98 | irq 0xe4 = 0x30 # power dram during S3 |
| 99 | end |
| 100 | device pnp 2e.b on # Hardware monitor |
| 101 | io 0x60 = 0x290 |
| 102 | end |
| 103 | device pnp 2e.c off end # PECI, SST |
| 104 | end |
| 105 | end |
| 106 | device pci 1f.1 on end # PATA/IDE |
| 107 | device pci 1f.2 on end # SATA |
Arthur Heymans | e4188a2 | 2017-09-07 17:05:57 +0200 | [diff] [blame] | 108 | device pci 1f.3 on # SMbus |
| 109 | chip drivers/i2c/ck505 # SLG8XP549T |
| 110 | register "mask" = "{ 0xff, 0xff, 0xff, |
| 111 | 0xff, 0xff, 0xff, 0xff, |
| 112 | 0xff, 0xff, 0xff, 0xff, |
| 113 | 0xff, 0xff }" |
| 114 | register "regs" = "{ 0x11, 0xd9, 0xff, |
| 115 | 0xfd, 0xff, 0x00, 0x00, |
| 116 | 0x06, 0x10, 0x05, 0x01, |
| 117 | 0x80, 0x0d }" |
| 118 | device i2c 69 on end |
| 119 | end |
| 120 | end |
Arthur Heymans | 2a4aada | 2017-04-12 13:53:08 +0200 | [diff] [blame] | 121 | device pci 1f.4 off end |
| 122 | device pci 1f.5 on end # IDE |
| 123 | device pci 1f.6 off end |
| 124 | end |
| 125 | end |
| 126 | end |