Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 1 | chip northbridge/intel/sandybridge |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 2 | # IGD Displays |
| 3 | register "gfx.ndid" = "3" |
| 4 | register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 5 | |
| 6 | # Enable DisplayPort Hotplug with 6ms pulse |
| 7 | register "gpu_dp_d_hotplug" = "0x06" |
| 8 | |
| 9 | # Enable Panel as LVDS and configure power delays |
| 10 | register "gpu_panel_port_select" = "0" # LVDS |
| 11 | register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms |
| 12 | register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms |
| 13 | register "gpu_panel_power_down_delay" = "150" # T3: 15ms |
| 14 | register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms |
| 15 | register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms |
| 16 | |
Vladimir Serbinenko | 93fc606 | 2016-01-31 13:21:04 +0100 | [diff] [blame] | 17 | # For native gfx |
| 18 | register "gfx.use_spread_spectrum_clock" = "0" |
| 19 | register "gfx.link_frequency_270_mhz" = "1" |
| 20 | register "gpu_cpu_backlight" = "0x1155" |
| 21 | register "gpu_pch_backlight" = "0x06100610" |
| 22 | |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 23 | register "max_mem_clock_mhz" = "666" |
| 24 | |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 25 | device cpu_cluster 0 on |
| 26 | chip cpu/intel/socket_rPGA989 |
| 27 | device lapic 0 on end |
| 28 | end |
| 29 | chip cpu/intel/model_206ax |
| 30 | # Magic APIC ID to locate this chip |
Arthur Heymans | b3f2323 | 2019-01-21 17:48:55 +0100 | [diff] [blame^] | 31 | device lapic 0xacac off end |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 32 | |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 33 | register "tcc_offset" = "5" # TCC of 95C |
| 34 | |
| 35 | register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) |
| 36 | register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) |
| 37 | register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) |
| 38 | |
| 39 | register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) |
| 40 | register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) |
| 41 | register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) |
| 42 | end |
| 43 | end |
| 44 | |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 45 | register "pci_mmio_size" = "1024" |
| 46 | |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 47 | device domain 0 on |
| 48 | subsystemid 0x1ae0 0xc000 inherit |
| 49 | device pci 00.0 on end # host bridge |
| 50 | device pci 02.0 on end # vga controller |
| 51 | |
| 52 | chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 53 | # GPI routing |
| 54 | # 0 No effect (default) |
| 55 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 56 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 57 | register "alt_gp_smi_en" = "0x0002" |
| 58 | register "gpi1_routing" = "1" |
| 59 | register "gpi6_routing" = "2" |
| 60 | |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 61 | register "sata_port_map" = "0x3" |
Shawn Nematbakhsh | 7b8952c | 2013-03-14 11:03:59 -0700 | [diff] [blame] | 62 | # Set max SATA speed to 3.0 Gb/s |
| 63 | register "sata_interface_speed_support" = "0x2" |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 64 | |
| 65 | # Enable EC Port 0x68/0x6C |
| 66 | register "gen1_dec" = "0x00040069" |
| 67 | |
| 68 | # EC range is 0x800-0x9ff |
| 69 | register "gen2_dec" = "0x00fc0901" |
| 70 | |
| 71 | # EC range is 0x1610-0x161F |
| 72 | register "gen3_dec" = "0x0001C1611" |
| 73 | |
| 74 | # Enable zero-based linear PCIe root port functions |
| 75 | register "pcie_port_coalesce" = "1" |
| 76 | |
Vladimir Serbinenko | 5b044ae | 2014-10-25 15:20:55 +0200 | [diff] [blame] | 77 | register "c2_latency" = "1" |
| 78 | register "p_cnt_throttling_supported" = "0" |
| 79 | |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 80 | device pci 14.0 on end # USB 3.0 Controller |
| 81 | device pci 16.0 on end # Management Engine Interface 1 |
| 82 | device pci 16.1 off end # Management Engine Interface 2 |
| 83 | device pci 16.2 off end # Management Engine IDE-R |
| 84 | device pci 16.3 off end # Management Engine KT |
| 85 | device pci 19.0 off end # Intel Gigabit Ethernet |
| 86 | device pci 1a.0 on end # USB2 EHCI #2 (AUO4, BlueTooth) |
| 87 | device pci 1b.0 on end # High Definition Audio |
| 88 | device pci 1c.0 on end # PCIe Port #1 |
| 89 | device pci 1c.1 on end # PCIe Port #2 (WLAN) |
| 90 | device pci 1c.2 on end # PCIe Port #3 (Card Reader) |
| 91 | register "pcie_aspm_f2" = "0x3" |
| 92 | device pci 1c.3 off end # PCIe Port #4 |
| 93 | device pci 1c.4 off end # PCIe Port #5 |
| 94 | device pci 1c.5 on end # PCIe Port #6 (LAN) |
| 95 | device pci 1c.6 off end # PCIe Port #7 |
| 96 | device pci 1c.7 off end # PCIe Port #8 |
| 97 | device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN) |
| 98 | device pci 1e.0 off end # PCI bridge |
| 99 | device pci 1f.0 on |
Matt DeVillier | 3044af7 | 2018-08-01 13:05:14 -0500 | [diff] [blame] | 100 | chip drivers/pc80/tpm |
| 101 | device pnp 0c31.0 on end |
| 102 | end |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 103 | chip ec/quanta/it8518 |
| 104 | # 60h/64h KBC |
| 105 | device pnp ff.1 on # dummy address |
| 106 | end |
| 107 | end |
| 108 | end # LPC bridge |
| 109 | device pci 1f.2 on end # SATA Controller 1 (HDD/SSD) |
| 110 | device pci 1f.3 on end # SMBus Controller |
| 111 | device pci 1f.5 off end # SATA Controller 2 (MSATA) |
| 112 | device pci 1f.6 off end # Thermal |
| 113 | end |
| 114 | end |
| 115 | end |