Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 DMP Electronics Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <pc80/mc146818rtc.h> |
Andrew Wu | 3fa1a13 | 2013-10-09 18:57:20 +0800 | [diff] [blame] | 26 | #include <pc80/keyboard.h> |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 27 | #include <string.h> |
Andrew Wu | 1fefa84 | 2013-10-24 20:37:48 +0800 | [diff] [blame] | 28 | #include <delay.h> |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 29 | #include "arch/io.h" |
| 30 | #include "chip.h" |
| 31 | #include "southbridge.h" |
Andrew Wu | 33b0956 | 2013-10-25 16:22:57 +0800 | [diff] [blame] | 32 | #include "cpu/dmp/dmp_post_code.h" |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 33 | |
| 34 | /* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */ |
| 35 | static const unsigned char irq_to_int_routing[16] = { |
| 36 | 0x0, 0x0, 0x0, 0x2, // IRQ0-2 is unmappable, IRQ3 = 2. |
| 37 | 0x4, 0x5, 0x7, 0x6, // IRQ4-7 = 4, 5, 7, 6. |
| 38 | 0x0, 0x1, 0x3, 0x9, // IRQ8 is unmappable, IRQ9-11 = 1, 3, 9. |
| 39 | 0xb, 0x0, 0xd, 0xf // IRQ12 = b, IRQ13 is unmappable, IRQ14-15 = d, f. |
| 40 | }; |
| 41 | |
| 42 | /* S/B PCI Interrupt routing table reg(0x58) field bit shift. */ |
| 43 | #define EHCIH_IRQ_SHIFT 28 |
| 44 | #define OHCII_IRQ_SHIFT 24 |
| 45 | #define MAC_IRQ_SHIFT 16 |
| 46 | #define RT3_IRQ_SHIFT 12 |
| 47 | #define RT2_IRQ_SHIFT 8 |
| 48 | #define RT1_IRQ_SHIFT 4 |
| 49 | #define RT0_IRQ_SHIFT 0 |
| 50 | |
| 51 | /* S/B Extend PCI Interrupt routing table reg(0xb4) field bit shift. */ |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 52 | #define CAN_IRQ_SHIFT 28 |
| 53 | #define HDA_IRQ_SHIFT 20 |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 54 | #define USBD_IRQ_SHIFT 16 |
| 55 | #define SIDE_IRQ_SHIFT 12 |
| 56 | #define PIDE_IRQ_SHIFT 8 |
| 57 | |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 58 | /* S/B function 1 Extend PCI Interrupt routing table reg 2(0xb4) |
| 59 | * field bit shift. |
| 60 | */ |
| 61 | #define SPI1_IRQ_SHIFT 8 |
| 62 | #define MOTOR_IRQ_SHIFT 0 |
| 63 | |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 64 | /* in-chip PCI device IRQs(0 for disabled). */ |
| 65 | #define EHCII_IRQ 5 |
| 66 | #define OHCII_IRQ 5 |
| 67 | #define MAC_IRQ 6 |
| 68 | |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 69 | #define CAN_IRQ 10 |
| 70 | #define HDA_IRQ 7 |
| 71 | #define USBD_IRQ 6 |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 72 | #define PIDE_IRQ 5 |
| 73 | |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 74 | #define SPI1_IRQ 10 |
Andrew Wu | a4ae310 | 2013-12-23 19:54:26 +0800 | [diff] [blame] | 75 | #define I2C0_IRQ 10 |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 76 | #define MOTOR_IRQ 11 |
| 77 | |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 78 | /* RT0-3 IRQs. */ |
| 79 | #define RT3_IRQ 3 |
| 80 | #define RT2_IRQ 4 |
| 81 | #define RT1_IRQ 5 |
| 82 | #define RT0_IRQ 6 |
| 83 | |
| 84 | /* IDE legacy mode IRQs. */ |
| 85 | #define IDE1_LEGACY_IRQ 14 |
| 86 | #define IDE2_LEGACY_IRQ 15 |
| 87 | |
| 88 | /* Internal parallel port */ |
| 89 | #define LPT_INT_C 0 |
| 90 | #define LPT_INT_ACK_SET 0 |
| 91 | #define LPT_UE 1 |
| 92 | #define LPT_PDMAS 0 |
| 93 | #define LPT_DREQS 0 |
| 94 | |
Andrew Wu | 1fefa84 | 2013-10-24 20:37:48 +0800 | [diff] [blame] | 95 | /* keyboard controller system flag timeout : 400 ms */ |
| 96 | #define KBC_TIMEOUT_SYS_FLAG 400 |
| 97 | |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 98 | static u8 get_pci_dev_func(device_t dev) |
| 99 | { |
| 100 | return PCI_FUNC(dev->path.pci.devfn); |
| 101 | } |
| 102 | |
| 103 | static void verify_dmp_keyboard_error(void) |
| 104 | { |
Andrew Wu | 33b0956 | 2013-10-25 16:22:57 +0800 | [diff] [blame] | 105 | post_code(POST_DMP_KBD_FW_VERIFY_ERR); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 106 | die("Internal keyboard firmware verify error!\n"); |
| 107 | } |
| 108 | |
| 109 | static void upload_dmp_keyboard_firmware(struct device *dev) |
| 110 | { |
| 111 | u32 reg_sb_c0; |
| 112 | u32 fwptr; |
| 113 | |
| 114 | // enable firmware uploading function by set bit 10. |
Andrew Wu | 33b0956 | 2013-10-25 16:22:57 +0800 | [diff] [blame] | 115 | post_code(POST_DMP_KBD_FW_UPLOAD); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 116 | reg_sb_c0 = pci_read_config32(dev, SB_REG_IPFCR); |
| 117 | pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 | 0x400); |
| 118 | |
| 119 | outw(0, 0x62); // reset upload address to 0. |
| 120 | // upload 4096 bytes from 0xFFFFE000. |
| 121 | outsb(0x66, (u8 *) 0xffffe000, 4096); |
| 122 | // upload 4096 bytes from 0xFFFFC000. |
| 123 | outsb(0x66, (u8 *) 0xffffc000, 4096); |
| 124 | |
| 125 | outw(0, 0x62); // reset upload address to 0. |
| 126 | // verify 4096 bytes from 0xFFFFE000. |
| 127 | for (fwptr = 0xffffe000; fwptr < 0xfffff000; fwptr++) { |
| 128 | if (inb(0x66) != *(u8 *) fwptr) { |
| 129 | verify_dmp_keyboard_error(); |
| 130 | } |
| 131 | } |
| 132 | // verify 4096 bytes from 0xFFFFC000. |
| 133 | for (fwptr = 0xffffc000; fwptr < 0xffffd000; fwptr++) { |
| 134 | if (inb(0x66) != *(u8 *) fwptr) { |
| 135 | verify_dmp_keyboard_error(); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | // disable firmware uploading. |
| 140 | pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L); |
Andrew Wu | 1ce4860 | 2013-10-19 01:33:08 +0800 | [diff] [blame] | 141 | } |
| 142 | |
Andrew Wu | 1fefa84 | 2013-10-24 20:37:48 +0800 | [diff] [blame] | 143 | static int kbc_wait_system_flag(void) |
Andrew Wu | 1ce4860 | 2013-10-19 01:33:08 +0800 | [diff] [blame] | 144 | { |
| 145 | /* wait keyboard controller ready by checking system flag |
| 146 | * (status port bit 2). |
| 147 | */ |
Andrew Wu | 33b0956 | 2013-10-25 16:22:57 +0800 | [diff] [blame] | 148 | post_code(POST_DMP_KBD_CHK_READY); |
Andrew Wu | 1fefa84 | 2013-10-24 20:37:48 +0800 | [diff] [blame] | 149 | u32 timeout; |
| 150 | for (timeout = KBC_TIMEOUT_SYS_FLAG; |
| 151 | timeout && ((inb(0x64) & 0x4) == 0); timeout--) |
| 152 | mdelay(1); |
| 153 | |
| 154 | if (!timeout) { |
| 155 | printk(BIOS_WARNING, "Keyboard controller system flag timeout\n"); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 156 | } |
Andrew Wu | 1fefa84 | 2013-10-24 20:37:48 +0800 | [diff] [blame] | 157 | return !!timeout; |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | static void pci_routing_fixup(struct device *dev) |
| 161 | { |
| 162 | const unsigned slot[3] = { 0 }; |
| 163 | const unsigned char slot_irqs[1][4] = { |
| 164 | {RT0_IRQ, RT1_IRQ, RT2_IRQ, RT3_IRQ}, |
| 165 | }; |
| 166 | const int slot_num = 1; |
| 167 | int i; |
| 168 | u32 int_routing = 0; |
| 169 | u32 ext_int_routing = 0; |
| 170 | |
| 171 | /* assign PCI-e bridge (bus#0, dev#1, fn#0) IRQ to RT0. */ |
| 172 | pci_assign_irqs(0, 1, slot_irqs[0]); |
| 173 | |
| 174 | /* RT0 is enabled. */ |
| 175 | int_routing |= irq_to_int_routing[RT0_IRQ] << RT0_IRQ_SHIFT; |
| 176 | |
| 177 | /* assign PCI slot IRQs. */ |
| 178 | for (i = 0; i < slot_num; i++) { |
| 179 | pci_assign_irqs(1, slot[i], slot_irqs[i]); |
| 180 | } |
| 181 | |
| 182 | /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ |
| 183 | for (i = 0; i < slot_num; i++) { |
| 184 | unsigned int funct; |
| 185 | device_t pdev; |
| 186 | u8 irq; |
| 187 | |
| 188 | /* Each slot may contain up to eight functions. */ |
| 189 | for (funct = 0; funct < 8; funct++) { |
| 190 | pdev = dev_find_slot(1, (slot[i] << 3) + funct); |
| 191 | if (!pdev) |
| 192 | continue; |
| 193 | irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE); |
| 194 | if (irq == RT1_IRQ) { |
| 195 | int_routing |= irq_to_int_routing[RT1_IRQ] << RT1_IRQ_SHIFT; |
| 196 | } else if (irq == RT2_IRQ) { |
| 197 | int_routing |= irq_to_int_routing[RT2_IRQ] << RT2_IRQ_SHIFT; |
| 198 | } else if (irq == RT3_IRQ) { |
| 199 | int_routing |= irq_to_int_routing[RT3_IRQ] << RT3_IRQ_SHIFT; |
| 200 | } |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | /* Setup S/B PCI Interrupt routing table reg(0x58). */ |
| 205 | int_routing |= irq_to_int_routing[EHCII_IRQ] << EHCIH_IRQ_SHIFT; |
| 206 | int_routing |= irq_to_int_routing[OHCII_IRQ] << OHCII_IRQ_SHIFT; |
| 207 | int_routing |= irq_to_int_routing[MAC_IRQ] << MAC_IRQ_SHIFT; |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 208 | pci_write_config32(dev, SB_REG_PIRQ_ROUTE, int_routing); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 209 | |
| 210 | /* Setup S/B PCI Extend Interrupt routing table reg(0xb4). */ |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 211 | ext_int_routing |= irq_to_int_routing[CAN_IRQ] << CAN_IRQ_SHIFT; |
| 212 | ext_int_routing |= irq_to_int_routing[HDA_IRQ] << HDA_IRQ_SHIFT; |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 213 | ext_int_routing |= irq_to_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT; |
| 214 | #if CONFIG_IDE_NATIVE_MODE |
| 215 | /* IDE in native mode, only uses one IRQ. */ |
| 216 | ext_int_routing |= irq_to_int_routing[0] << SIDE_IRQ_SHIFT; |
| 217 | ext_int_routing |= irq_to_int_routing[PIDE_IRQ] << PIDE_IRQ_SHIFT; |
| 218 | #else |
| 219 | /* IDE in legacy mode, use IRQ 14, 15. */ |
| 220 | ext_int_routing |= irq_to_int_routing[IDE2_LEGACY_IRQ] << SIDE_IRQ_SHIFT; |
| 221 | ext_int_routing |= irq_to_int_routing[IDE1_LEGACY_IRQ] << PIDE_IRQ_SHIFT; |
| 222 | #endif |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 223 | pci_write_config32(dev, SB_REG_EXT_PIRQ_ROUTE, ext_int_routing); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 224 | |
| 225 | /* Assign in-chip PCI device IRQs. */ |
| 226 | if (MAC_IRQ) { |
| 227 | unsigned char irqs[4] = { MAC_IRQ, 0, 0, 0 }; |
| 228 | pci_assign_irqs(0, 0x8, irqs); |
| 229 | } |
| 230 | if (OHCII_IRQ && EHCII_IRQ) { |
| 231 | unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 }; |
| 232 | pci_assign_irqs(0, 0xa, irqs); |
| 233 | } |
| 234 | if (CONFIG_IDE_NATIVE_MODE && PIDE_IRQ) { |
| 235 | /* IDE in native mode, setup PCI IRQ. */ |
| 236 | unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 }; |
| 237 | pci_assign_irqs(0, 0xc, irqs); |
| 238 | } |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 239 | if (CAN_IRQ) { |
| 240 | unsigned char irqs[4] = { CAN_IRQ, 0, 0, 0 }; |
| 241 | pci_assign_irqs(0, 0x11, irqs); |
| 242 | } |
| 243 | if (HDA_IRQ) { |
| 244 | unsigned char irqs[4] = { HDA_IRQ, 0, 0, 0 }; |
| 245 | pci_assign_irqs(0, 0xe, irqs); |
| 246 | } |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 247 | if (USBD_IRQ) { |
| 248 | unsigned char irqs[4] = { USBD_IRQ, 0, 0, 0 }; |
| 249 | pci_assign_irqs(0, 0xf, irqs); |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | static void vortex_sb_init(struct device *dev) |
| 254 | { |
| 255 | u32 lpt_reg = 0; |
| 256 | |
| 257 | #if CONFIG_LPT_ENABLE |
| 258 | int ppmod = 0; |
| 259 | #if CONFIG_LPT_MODE_BPP |
| 260 | ppmod = 0; |
| 261 | #elif CONFIG_LPT_MODE_EPP_19_AND_SPP |
| 262 | ppmod = 1; |
| 263 | #elif CONFIG_LPT_MODE_ECP |
| 264 | ppmod = 2; |
| 265 | #elif CONFIG_LPT_MODE_ECP_AND_EPP_19 |
| 266 | ppmod = 3; |
| 267 | #elif CONFIG_LPT_MODE_SPP |
| 268 | ppmod = 4; |
| 269 | #elif CONFIG_LPT_MODE_EPP_17_AND_SPP |
| 270 | ppmod = 5; |
| 271 | #elif CONFIG_LPT_MODE_ECP_AND_EPP_17 |
| 272 | ppmod = 7; |
| 273 | #else |
| 274 | #error CONFIG_LPT_MODE error. |
| 275 | #endif |
| 276 | |
| 277 | /* Setup internal parallel port */ |
| 278 | lpt_reg |= (LPT_INT_C << 28); |
| 279 | lpt_reg |= (LPT_INT_ACK_SET << 27); |
| 280 | lpt_reg |= (ppmod << 24); |
| 281 | lpt_reg |= (LPT_UE << 23); |
| 282 | lpt_reg |= (LPT_PDMAS << 22); |
| 283 | lpt_reg |= (LPT_DREQS << 20); |
| 284 | lpt_reg |= (irq_to_int_routing[CONFIG_LPT_IRQ] << 16); |
| 285 | lpt_reg |= (CONFIG_LPT_IO << 0); |
| 286 | #endif // CONFIG_LPT_ENABLE |
| 287 | pci_write_config32(dev, SB_REG_IPPCR, lpt_reg); |
| 288 | } |
| 289 | |
| 290 | #define SETUP_GPIO_ADDR(n) \ |
| 291 | u32 cfg##n = (CONFIG_GPIO_P##n##_DIR_ADDR << 16) | (CONFIG_GPIO_P##n##_DATA_ADDR);\ |
| 292 | outl(cfg##n, base + 4 + (n * 4));\ |
| 293 | gpio_enable_mask |= (1 << n); |
| 294 | |
| 295 | #define INIT_GPIO(n) \ |
| 296 | outb(CONFIG_GPIO_P##n##_INIT_DIR, CONFIG_GPIO_P##n##_DIR_ADDR);\ |
| 297 | outb(CONFIG_GPIO_P##n##_INIT_DATA, CONFIG_GPIO_P##n##_DATA_ADDR); |
| 298 | |
| 299 | static void ex_sb_gpio_init(struct device *dev) |
| 300 | { |
| 301 | const int base = 0xb00; |
| 302 | u32 gpio_enable_mask = 0; |
| 303 | /* S/B register 63h - 62h : GPIO Port Config IO Base Address */ |
| 304 | pci_write_config16(dev, SB_REG_GPIO_CFG_IO_BASE, base | 1); |
| 305 | /* Set GPIO port 0~9 base address. |
| 306 | * Config Base + 04h, 08h, 0ch... : GPIO port 0~9 data/dir decode addr. |
| 307 | * Bit 31-16 : DBA, GPIO direction base address. |
| 308 | * Bit 15-0 : DPBA, GPIO data port base address. |
| 309 | * */ |
| 310 | #if CONFIG_GPIO_P0_ENABLE |
| 311 | SETUP_GPIO_ADDR(0) |
| 312 | #endif |
| 313 | #if CONFIG_GPIO_P1_ENABLE |
| 314 | SETUP_GPIO_ADDR(1) |
| 315 | #endif |
| 316 | #if CONFIG_GPIO_P2_ENABLE |
| 317 | SETUP_GPIO_ADDR(2) |
| 318 | #endif |
| 319 | #if CONFIG_GPIO_P3_ENABLE |
| 320 | SETUP_GPIO_ADDR(3) |
| 321 | #endif |
| 322 | #if CONFIG_GPIO_P4_ENABLE |
| 323 | SETUP_GPIO_ADDR(4) |
| 324 | #endif |
| 325 | #if CONFIG_GPIO_P5_ENABLE |
| 326 | SETUP_GPIO_ADDR(5) |
| 327 | #endif |
| 328 | #if CONFIG_GPIO_P6_ENABLE |
| 329 | SETUP_GPIO_ADDR(6) |
| 330 | #endif |
| 331 | #if CONFIG_GPIO_P7_ENABLE |
| 332 | SETUP_GPIO_ADDR(7) |
| 333 | #endif |
| 334 | #if CONFIG_GPIO_P8_ENABLE |
| 335 | SETUP_GPIO_ADDR(8) |
| 336 | #endif |
| 337 | #if CONFIG_GPIO_P9_ENABLE |
| 338 | SETUP_GPIO_ADDR(9) |
| 339 | #endif |
| 340 | /* Enable GPIO port 0~9. */ |
| 341 | outl(gpio_enable_mask, base); |
| 342 | /* Set GPIO port 0-9 initial dir and data. */ |
| 343 | #if CONFIG_GPIO_P0_ENABLE |
| 344 | INIT_GPIO(0) |
| 345 | #endif |
| 346 | #if CONFIG_GPIO_P1_ENABLE |
| 347 | INIT_GPIO(1) |
| 348 | #endif |
| 349 | #if CONFIG_GPIO_P2_ENABLE |
| 350 | INIT_GPIO(2) |
| 351 | #endif |
| 352 | #if CONFIG_GPIO_P3_ENABLE |
| 353 | INIT_GPIO(3) |
| 354 | #endif |
| 355 | #if CONFIG_GPIO_P4_ENABLE |
| 356 | INIT_GPIO(4) |
| 357 | #endif |
| 358 | #if CONFIG_GPIO_P5_ENABLE |
| 359 | INIT_GPIO(5) |
| 360 | #endif |
| 361 | #if CONFIG_GPIO_P6_ENABLE |
| 362 | INIT_GPIO(6) |
| 363 | #endif |
| 364 | #if CONFIG_GPIO_P7_ENABLE |
| 365 | INIT_GPIO(7) |
| 366 | #endif |
| 367 | #if CONFIG_GPIO_P8_ENABLE |
| 368 | INIT_GPIO(8) |
| 369 | #endif |
| 370 | #if CONFIG_GPIO_P9_ENABLE |
| 371 | INIT_GPIO(9) |
| 372 | #endif |
| 373 | /* Disable GPIO Port Config IO Base Address. */ |
| 374 | pci_write_config16(dev, SB_REG_GPIO_CFG_IO_BASE, 0x0); |
| 375 | } |
| 376 | |
| 377 | static u32 make_uart_config(u16 base, u8 irq) |
| 378 | { |
| 379 | u8 mapped_irq = irq_to_int_routing[irq]; |
| 380 | u32 cfg = 0; |
| 381 | cfg |= 1 << 23; // UE = enabled. |
| 382 | cfg |= (mapped_irq << 16); // UIRT. |
| 383 | cfg |= base; // UIOA. |
| 384 | return cfg; |
| 385 | } |
| 386 | |
| 387 | #define SETUP_UART(n) \ |
| 388 | uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\ |
Kyösti Mälkki | a4c7b7a | 2014-02-16 06:55:41 +0200 | [diff] [blame] | 389 | outl(uart_cfg, base + (n - 1) * 4); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 390 | |
| 391 | static void ex_sb_uart_init(struct device *dev) |
| 392 | { |
| 393 | const int base = 0xc00; |
| 394 | u32 uart_cfg = 0; |
| 395 | /* S/B register 61h - 60h : UART Config IO Base Address */ |
| 396 | pci_write_config16(dev, SB_REG_UART_CFG_IO_BASE, base | 1); |
| 397 | /* setup UART */ |
| 398 | #if CONFIG_UART1_ENABLE |
| 399 | SETUP_UART(1) |
| 400 | #endif |
| 401 | #if CONFIG_UART2_ENABLE |
| 402 | SETUP_UART(2) |
| 403 | #endif |
| 404 | #if CONFIG_UART3_ENABLE |
| 405 | SETUP_UART(3) |
| 406 | #endif |
| 407 | #if CONFIG_UART4_ENABLE |
| 408 | SETUP_UART(4) |
| 409 | #endif |
| 410 | #if CONFIG_UART5_ENABLE |
| 411 | SETUP_UART(5) |
| 412 | #endif |
| 413 | #if CONFIG_UART6_ENABLE |
| 414 | SETUP_UART(6) |
| 415 | #endif |
| 416 | #if CONFIG_UART7_ENABLE |
| 417 | SETUP_UART(7) |
| 418 | #endif |
| 419 | #if CONFIG_UART8_ENABLE |
| 420 | SETUP_UART(8) |
| 421 | #endif |
| 422 | #if CONFIG_UART9_ENABLE |
| 423 | SETUP_UART(9) |
| 424 | #endif |
| 425 | #if CONFIG_UART10_ENABLE |
| 426 | SETUP_UART(10) |
| 427 | #endif |
| 428 | /* Keep UART Config I/O base address */ |
| 429 | //pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0); |
| 430 | } |
| 431 | |
Andrew Wu | a4ae310 | 2013-12-23 19:54:26 +0800 | [diff] [blame] | 432 | static void i2c_init(struct device *dev) |
| 433 | { |
| 434 | u8 mapped_irq = irq_to_int_routing[I2C0_IRQ]; |
| 435 | u32 cfg = 0; |
| 436 | cfg |= 1 << 31; // UE = enabled. |
| 437 | cfg |= (mapped_irq << 16); // IIRT0. |
| 438 | cfg |= CONFIG_I2C_BASE; // UIOA. |
| 439 | pci_write_config32(dev, SB_REG_II2CCR, cfg); |
| 440 | } |
| 441 | |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 442 | static int get_rtc_update_in_progress(void) |
| 443 | { |
| 444 | if (cmos_read(RTC_REG_A) & RTC_UIP) |
| 445 | return 1; |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | static void unsafe_read_cmos_rtc(u8 rtc[7]) |
| 450 | { |
| 451 | rtc[0] = cmos_read(RTC_CLK_ALTCENTURY); |
| 452 | rtc[1] = cmos_read(RTC_CLK_YEAR); |
| 453 | rtc[2] = cmos_read(RTC_CLK_MONTH); |
| 454 | rtc[3] = cmos_read(RTC_CLK_DAYOFMONTH); |
| 455 | rtc[4] = cmos_read(RTC_CLK_HOUR); |
| 456 | rtc[5] = cmos_read(RTC_CLK_MINUTE); |
| 457 | rtc[6] = cmos_read(RTC_CLK_SECOND); |
| 458 | } |
| 459 | |
| 460 | static void read_cmos_rtc(u8 rtc[7]) |
| 461 | { |
| 462 | /* Read RTC twice and check update-in-progress flag, to make |
| 463 | * sure RTC is correct */ |
| 464 | u8 rtc_old[7], rtc_new[7]; |
| 465 | while (get_rtc_update_in_progress()) ; |
| 466 | unsafe_read_cmos_rtc(rtc_new); |
| 467 | do { |
| 468 | memcpy(rtc_old, rtc_new, 7); |
| 469 | while (get_rtc_update_in_progress()) ; |
| 470 | unsafe_read_cmos_rtc(rtc_new); |
| 471 | } while (memcmp(rtc_new, rtc_old, 7) != 0); |
| 472 | } |
| 473 | |
| 474 | /* |
| 475 | * Convert a number in decimal format into the BCD format. |
| 476 | * Return 255 if not a valid BCD value. |
| 477 | */ |
| 478 | static u8 bcd2dec(u8 bcd) |
| 479 | { |
| 480 | u8 h, l; |
| 481 | h = bcd >> 4; |
| 482 | l = bcd & 0xf; |
| 483 | if (h > 9 || l > 9) |
| 484 | return 255; |
| 485 | return h * 10 + l; |
| 486 | } |
| 487 | |
| 488 | static void fix_cmos_rtc_time(void) |
| 489 | { |
| 490 | /* Read RTC data. */ |
| 491 | u8 rtc[7]; |
| 492 | read_cmos_rtc(rtc); |
| 493 | |
| 494 | /* Convert RTC from BCD format to binary. */ |
| 495 | u8 bin_rtc[7]; |
| 496 | int i; |
Daniele Forsi | c2519e5 | 2014-07-26 11:17:03 +0200 | [diff] [blame] | 497 | for (i = 0; i < 7; i++) { |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 498 | bin_rtc[i] = bcd2dec(rtc[i]); |
| 499 | } |
| 500 | |
| 501 | /* If RTC date is invalid, fix it. */ |
| 502 | if (bin_rtc[0] > 99 || bin_rtc[1] > 99 || bin_rtc[2] > 12 || bin_rtc[3] > 31) { |
| 503 | /* Set PC compatible timing mode. */ |
| 504 | cmos_write(0x26, RTC_REG_A); |
| 505 | cmos_write(0x02, RTC_REG_B); |
| 506 | /* Now setup a default date 2008/08/08 08:08:08. */ |
| 507 | cmos_write(0x8, RTC_CLK_SECOND); |
| 508 | cmos_write(0x8, RTC_CLK_MINUTE); |
| 509 | cmos_write(0x8, RTC_CLK_HOUR); |
| 510 | cmos_write(0x6, RTC_CLK_DAYOFWEEK); /* Friday */ |
| 511 | cmos_write(0x8, RTC_CLK_DAYOFMONTH); |
| 512 | cmos_write(0x8, RTC_CLK_MONTH); |
| 513 | cmos_write(0x8, RTC_CLK_YEAR); |
| 514 | cmos_write(0x20, RTC_CLK_ALTCENTURY); |
| 515 | } |
| 516 | } |
| 517 | |
Andrew Wu | fea5b50 | 2013-10-31 20:12:09 +0800 | [diff] [blame] | 518 | static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 519 | { |
| 520 | struct resource *res; |
Andrew Wu | fea5b50 | 2013-10-31 20:12:09 +0800 | [diff] [blame] | 521 | res = new_resource(dev, index); |
| 522 | res->base = base; |
| 523 | res->size = size; |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 524 | res->limit = 0xffffUL; |
| 525 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 526 | } |
| 527 | |
Andrew Wu | fea5b50 | 2013-10-31 20:12:09 +0800 | [diff] [blame] | 528 | static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 529 | { |
| 530 | /* SPI flash is in topmost of 4G memory space */ |
| 531 | struct resource *res; |
Andrew Wu | fea5b50 | 2013-10-31 20:12:09 +0800 | [diff] [blame] | 532 | res = new_resource(dev, index); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 533 | res->base = 0x100000000LL - flash_size; |
| 534 | res->size = flash_size; |
| 535 | res->limit = 0xffffffffUL; |
| 536 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 537 | } |
| 538 | |
| 539 | static void vortex86_sb_read_resources(device_t dev) |
| 540 | { |
| 541 | u32 flash_size = 8 * 1024 * 1024; |
| 542 | |
| 543 | pci_dev_read_resources(dev); |
| 544 | |
| 545 | if (dev->device == 0x6011) { |
| 546 | /* It is EX CPU southbridge */ |
| 547 | if (get_pci_dev_func(dev) != 0) { |
| 548 | /* only for function 0, skip function 1 */ |
| 549 | return; |
| 550 | } |
| 551 | /* default SPI flash ROM is 64MB */ |
| 552 | flash_size = 64 * 1024 * 1024; |
| 553 | } |
| 554 | |
Andrew Wu | fea5b50 | 2013-10-31 20:12:09 +0800 | [diff] [blame] | 555 | /* Reserve space for legacy I/O */ |
| 556 | vortex86_sb_set_io_resv(dev, 1, 0, 0x1000UL); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 557 | |
| 558 | /* Reserve space for flash */ |
Andrew Wu | fea5b50 | 2013-10-31 20:12:09 +0800 | [diff] [blame] | 559 | vortex86_sb_set_spi_flash_size(dev, 2, flash_size); |
Andrew Wu | a4ae310 | 2013-12-23 19:54:26 +0800 | [diff] [blame] | 560 | |
| 561 | /* Reserve space for I2C */ |
| 562 | vortex86_sb_set_io_resv(dev, 3, CONFIG_I2C_BASE, 8); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 563 | } |
| 564 | |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 565 | static void southbridge_init_func1(struct device *dev) |
| 566 | { |
| 567 | /* Handle S/B function 1 PCI IRQ routing. (SPI1/MOTOR) */ |
| 568 | u32 ext_int_routing2 = 0; |
| 569 | /* Setup S/B function 1 PCI Extend Interrupt routing table reg 2(0xb4). */ |
| 570 | ext_int_routing2 |= irq_to_int_routing[SPI1_IRQ] << SPI1_IRQ_SHIFT; |
| 571 | ext_int_routing2 |= irq_to_int_routing[MOTOR_IRQ] << MOTOR_IRQ_SHIFT; |
| 572 | pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2); |
| 573 | |
| 574 | /* Assign in-chip PCI device IRQs. */ |
| 575 | if (SPI1_IRQ || MOTOR_IRQ) { |
| 576 | unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 }; |
| 577 | pci_assign_irqs(0, 0x10, irqs); |
| 578 | } |
| 579 | } |
| 580 | |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 581 | static void southbridge_init(struct device *dev) |
| 582 | { |
Andrew Wu | 5291432 | 2013-07-09 21:29:25 +0800 | [diff] [blame] | 583 | /* Check it is function 0 or 1. (Same Vendor/Device ID) */ |
| 584 | if (get_pci_dev_func(dev) != 0) { |
| 585 | southbridge_init_func1(dev); |
| 586 | return; |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 587 | } |
| 588 | upload_dmp_keyboard_firmware(dev); |
| 589 | vortex_sb_init(dev); |
| 590 | if (dev->device == 0x6011) { |
| 591 | ex_sb_gpio_init(dev); |
| 592 | ex_sb_uart_init(dev); |
Andrew Wu | a4ae310 | 2013-12-23 19:54:26 +0800 | [diff] [blame] | 593 | i2c_init(dev); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 594 | } |
| 595 | pci_routing_fixup(dev); |
| 596 | |
| 597 | fix_cmos_rtc_time(); |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame^] | 598 | cmos_init(0); |
Andrew Wu | 1fefa84 | 2013-10-24 20:37:48 +0800 | [diff] [blame] | 599 | /* Check keyboard controller ready. If timeout, reload firmware code |
| 600 | * and try again. |
| 601 | */ |
| 602 | u32 retries = 10; |
| 603 | while (!kbc_wait_system_flag()) { |
| 604 | if (!retries) { |
| 605 | post_code(POST_DMP_KBD_IS_BAD); |
| 606 | die("The keyboard timeout occurred too often. " |
| 607 | "Your CPU is probably defect. " |
| 608 | "Contact your dealer to replace it\n"); |
| 609 | } |
| 610 | upload_dmp_keyboard_firmware(dev); |
| 611 | retries--; |
| 612 | } |
| 613 | post_code(POST_DMP_KBD_IS_READY); |
Edward O'Callaghan | def00be | 2014-04-30 05:01:52 +1000 | [diff] [blame] | 614 | pc_keyboard_init(); |
Andrew Wu | 00bf647 | 2013-06-26 21:24:59 +0800 | [diff] [blame] | 615 | } |
| 616 | |
| 617 | static struct device_operations vortex_sb_ops = { |
| 618 | .read_resources = vortex86_sb_read_resources, |
| 619 | .set_resources = pci_dev_set_resources, |
| 620 | .enable_resources = pci_dev_enable_resources, |
| 621 | .init = &southbridge_init, |
| 622 | .scan_bus = scan_static_bus, |
| 623 | .enable = 0, |
| 624 | .ops_pci = 0, |
| 625 | }; |
| 626 | |
| 627 | static const struct pci_driver pci_driver_6011 __pci_driver = { |
| 628 | .ops = &vortex_sb_ops, |
| 629 | .vendor = PCI_VENDOR_ID_RDC, |
| 630 | .device = 0x6011, /* EX CPU S/B ID */ |
| 631 | }; |
| 632 | |
| 633 | struct chip_operations southbridge_dmp_vortex86ex_ops = { |
| 634 | CHIP_NAME("DMP Vortex86EX Southbridge") |
| 635 | .enable_dev = 0 |
| 636 | }; |