blob: 5be857582b20be8fdcc0a29aaccc8df2bf807b86 [file] [log] [blame]
Andrew Wu00bf6472013-06-26 21:24:59 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 DMP Electronics Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <console/console.h>
21#include <device/device.h>
22#include <device/pci.h>
23#include <device/pci_ops.h>
24#include <device/pci_ids.h>
25#include <pc80/mc146818rtc.h>
Andrew Wu3fa1a132013-10-09 18:57:20 +080026#include <pc80/keyboard.h>
Andrew Wu00bf6472013-06-26 21:24:59 +080027#include <string.h>
Andrew Wu1fefa842013-10-24 20:37:48 +080028#include <delay.h>
Andrew Wu00bf6472013-06-26 21:24:59 +080029#include "arch/io.h"
30#include "chip.h"
31#include "southbridge.h"
Andrew Wu33b09562013-10-25 16:22:57 +080032#include "cpu/dmp/dmp_post_code.h"
Andrew Wu00bf6472013-06-26 21:24:59 +080033
34/* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */
35static const unsigned char irq_to_int_routing[16] = {
36 0x0, 0x0, 0x0, 0x2, // IRQ0-2 is unmappable, IRQ3 = 2.
37 0x4, 0x5, 0x7, 0x6, // IRQ4-7 = 4, 5, 7, 6.
38 0x0, 0x1, 0x3, 0x9, // IRQ8 is unmappable, IRQ9-11 = 1, 3, 9.
39 0xb, 0x0, 0xd, 0xf // IRQ12 = b, IRQ13 is unmappable, IRQ14-15 = d, f.
40};
41
42/* S/B PCI Interrupt routing table reg(0x58) field bit shift. */
43#define EHCIH_IRQ_SHIFT 28
44#define OHCII_IRQ_SHIFT 24
45#define MAC_IRQ_SHIFT 16
46#define RT3_IRQ_SHIFT 12
47#define RT2_IRQ_SHIFT 8
48#define RT1_IRQ_SHIFT 4
49#define RT0_IRQ_SHIFT 0
50
51/* S/B Extend PCI Interrupt routing table reg(0xb4) field bit shift. */
Andrew Wu52914322013-07-09 21:29:25 +080052#define CAN_IRQ_SHIFT 28
53#define HDA_IRQ_SHIFT 20
Andrew Wu00bf6472013-06-26 21:24:59 +080054#define USBD_IRQ_SHIFT 16
55#define SIDE_IRQ_SHIFT 12
56#define PIDE_IRQ_SHIFT 8
57
Andrew Wu52914322013-07-09 21:29:25 +080058/* S/B function 1 Extend PCI Interrupt routing table reg 2(0xb4)
59 * field bit shift.
60 */
61#define SPI1_IRQ_SHIFT 8
62#define MOTOR_IRQ_SHIFT 0
63
Andrew Wu00bf6472013-06-26 21:24:59 +080064/* in-chip PCI device IRQs(0 for disabled). */
65#define EHCII_IRQ 5
66#define OHCII_IRQ 5
67#define MAC_IRQ 6
68
Andrew Wu52914322013-07-09 21:29:25 +080069#define CAN_IRQ 10
70#define HDA_IRQ 7
71#define USBD_IRQ 6
Andrew Wu00bf6472013-06-26 21:24:59 +080072#define PIDE_IRQ 5
73
Andrew Wu52914322013-07-09 21:29:25 +080074#define SPI1_IRQ 10
75#define MOTOR_IRQ 11
76
Andrew Wu00bf6472013-06-26 21:24:59 +080077/* RT0-3 IRQs. */
78#define RT3_IRQ 3
79#define RT2_IRQ 4
80#define RT1_IRQ 5
81#define RT0_IRQ 6
82
83/* IDE legacy mode IRQs. */
84#define IDE1_LEGACY_IRQ 14
85#define IDE2_LEGACY_IRQ 15
86
87/* Internal parallel port */
88#define LPT_INT_C 0
89#define LPT_INT_ACK_SET 0
90#define LPT_UE 1
91#define LPT_PDMAS 0
92#define LPT_DREQS 0
93
Andrew Wu1fefa842013-10-24 20:37:48 +080094/* keyboard controller system flag timeout : 400 ms */
95#define KBC_TIMEOUT_SYS_FLAG 400
96
Andrew Wu00bf6472013-06-26 21:24:59 +080097static u8 get_pci_dev_func(device_t dev)
98{
99 return PCI_FUNC(dev->path.pci.devfn);
100}
101
102static void verify_dmp_keyboard_error(void)
103{
Andrew Wu33b09562013-10-25 16:22:57 +0800104 post_code(POST_DMP_KBD_FW_VERIFY_ERR);
Andrew Wu00bf6472013-06-26 21:24:59 +0800105 die("Internal keyboard firmware verify error!\n");
106}
107
108static void upload_dmp_keyboard_firmware(struct device *dev)
109{
110 u32 reg_sb_c0;
111 u32 fwptr;
112
113 // enable firmware uploading function by set bit 10.
Andrew Wu33b09562013-10-25 16:22:57 +0800114 post_code(POST_DMP_KBD_FW_UPLOAD);
Andrew Wu00bf6472013-06-26 21:24:59 +0800115 reg_sb_c0 = pci_read_config32(dev, SB_REG_IPFCR);
116 pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 | 0x400);
117
118 outw(0, 0x62); // reset upload address to 0.
119 // upload 4096 bytes from 0xFFFFE000.
120 outsb(0x66, (u8 *) 0xffffe000, 4096);
121 // upload 4096 bytes from 0xFFFFC000.
122 outsb(0x66, (u8 *) 0xffffc000, 4096);
123
124 outw(0, 0x62); // reset upload address to 0.
125 // verify 4096 bytes from 0xFFFFE000.
126 for (fwptr = 0xffffe000; fwptr < 0xfffff000; fwptr++) {
127 if (inb(0x66) != *(u8 *) fwptr) {
128 verify_dmp_keyboard_error();
129 }
130 }
131 // verify 4096 bytes from 0xFFFFC000.
132 for (fwptr = 0xffffc000; fwptr < 0xffffd000; fwptr++) {
133 if (inb(0x66) != *(u8 *) fwptr) {
134 verify_dmp_keyboard_error();
135 }
136 }
137
138 // disable firmware uploading.
139 pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L);
Andrew Wu1ce48602013-10-19 01:33:08 +0800140}
141
Andrew Wu1fefa842013-10-24 20:37:48 +0800142static int kbc_wait_system_flag(void)
Andrew Wu1ce48602013-10-19 01:33:08 +0800143{
144 /* wait keyboard controller ready by checking system flag
145 * (status port bit 2).
146 */
Andrew Wu33b09562013-10-25 16:22:57 +0800147 post_code(POST_DMP_KBD_CHK_READY);
Andrew Wu1fefa842013-10-24 20:37:48 +0800148 u32 timeout;
149 for (timeout = KBC_TIMEOUT_SYS_FLAG;
150 timeout && ((inb(0x64) & 0x4) == 0); timeout--)
151 mdelay(1);
152
153 if (!timeout) {
154 printk(BIOS_WARNING, "Keyboard controller system flag timeout\n");
Andrew Wu00bf6472013-06-26 21:24:59 +0800155 }
Andrew Wu1fefa842013-10-24 20:37:48 +0800156 return !!timeout;
Andrew Wu00bf6472013-06-26 21:24:59 +0800157}
158
159static void pci_routing_fixup(struct device *dev)
160{
161 const unsigned slot[3] = { 0 };
162 const unsigned char slot_irqs[1][4] = {
163 {RT0_IRQ, RT1_IRQ, RT2_IRQ, RT3_IRQ},
164 };
165 const int slot_num = 1;
166 int i;
167 u32 int_routing = 0;
168 u32 ext_int_routing = 0;
169
170 /* assign PCI-e bridge (bus#0, dev#1, fn#0) IRQ to RT0. */
171 pci_assign_irqs(0, 1, slot_irqs[0]);
172
173 /* RT0 is enabled. */
174 int_routing |= irq_to_int_routing[RT0_IRQ] << RT0_IRQ_SHIFT;
175
176 /* assign PCI slot IRQs. */
177 for (i = 0; i < slot_num; i++) {
178 pci_assign_irqs(1, slot[i], slot_irqs[i]);
179 }
180
181 /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */
182 for (i = 0; i < slot_num; i++) {
183 unsigned int funct;
184 device_t pdev;
185 u8 irq;
186
187 /* Each slot may contain up to eight functions. */
188 for (funct = 0; funct < 8; funct++) {
189 pdev = dev_find_slot(1, (slot[i] << 3) + funct);
190 if (!pdev)
191 continue;
192 irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
193 if (irq == RT1_IRQ) {
194 int_routing |= irq_to_int_routing[RT1_IRQ] << RT1_IRQ_SHIFT;
195 } else if (irq == RT2_IRQ) {
196 int_routing |= irq_to_int_routing[RT2_IRQ] << RT2_IRQ_SHIFT;
197 } else if (irq == RT3_IRQ) {
198 int_routing |= irq_to_int_routing[RT3_IRQ] << RT3_IRQ_SHIFT;
199 }
200 }
201 }
202
203 /* Setup S/B PCI Interrupt routing table reg(0x58). */
204 int_routing |= irq_to_int_routing[EHCII_IRQ] << EHCIH_IRQ_SHIFT;
205 int_routing |= irq_to_int_routing[OHCII_IRQ] << OHCII_IRQ_SHIFT;
206 int_routing |= irq_to_int_routing[MAC_IRQ] << MAC_IRQ_SHIFT;
Andrew Wu52914322013-07-09 21:29:25 +0800207 pci_write_config32(dev, SB_REG_PIRQ_ROUTE, int_routing);
Andrew Wu00bf6472013-06-26 21:24:59 +0800208
209 /* Setup S/B PCI Extend Interrupt routing table reg(0xb4). */
Andrew Wu52914322013-07-09 21:29:25 +0800210 ext_int_routing |= irq_to_int_routing[CAN_IRQ] << CAN_IRQ_SHIFT;
211 ext_int_routing |= irq_to_int_routing[HDA_IRQ] << HDA_IRQ_SHIFT;
Andrew Wu00bf6472013-06-26 21:24:59 +0800212 ext_int_routing |= irq_to_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT;
213#if CONFIG_IDE_NATIVE_MODE
214 /* IDE in native mode, only uses one IRQ. */
215 ext_int_routing |= irq_to_int_routing[0] << SIDE_IRQ_SHIFT;
216 ext_int_routing |= irq_to_int_routing[PIDE_IRQ] << PIDE_IRQ_SHIFT;
217#else
218 /* IDE in legacy mode, use IRQ 14, 15. */
219 ext_int_routing |= irq_to_int_routing[IDE2_LEGACY_IRQ] << SIDE_IRQ_SHIFT;
220 ext_int_routing |= irq_to_int_routing[IDE1_LEGACY_IRQ] << PIDE_IRQ_SHIFT;
221#endif
Andrew Wu52914322013-07-09 21:29:25 +0800222 pci_write_config32(dev, SB_REG_EXT_PIRQ_ROUTE, ext_int_routing);
Andrew Wu00bf6472013-06-26 21:24:59 +0800223
224 /* Assign in-chip PCI device IRQs. */
225 if (MAC_IRQ) {
226 unsigned char irqs[4] = { MAC_IRQ, 0, 0, 0 };
227 pci_assign_irqs(0, 0x8, irqs);
228 }
229 if (OHCII_IRQ && EHCII_IRQ) {
230 unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 };
231 pci_assign_irqs(0, 0xa, irqs);
232 }
233 if (CONFIG_IDE_NATIVE_MODE && PIDE_IRQ) {
234 /* IDE in native mode, setup PCI IRQ. */
235 unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 };
236 pci_assign_irqs(0, 0xc, irqs);
237 }
Andrew Wu52914322013-07-09 21:29:25 +0800238 if (CAN_IRQ) {
239 unsigned char irqs[4] = { CAN_IRQ, 0, 0, 0 };
240 pci_assign_irqs(0, 0x11, irqs);
241 }
242 if (HDA_IRQ) {
243 unsigned char irqs[4] = { HDA_IRQ, 0, 0, 0 };
244 pci_assign_irqs(0, 0xe, irqs);
245 }
Andrew Wu00bf6472013-06-26 21:24:59 +0800246 if (USBD_IRQ) {
247 unsigned char irqs[4] = { USBD_IRQ, 0, 0, 0 };
248 pci_assign_irqs(0, 0xf, irqs);
249 }
250}
251
252static void vortex_sb_init(struct device *dev)
253{
254 u32 lpt_reg = 0;
255
256#if CONFIG_LPT_ENABLE
257 int ppmod = 0;
258#if CONFIG_LPT_MODE_BPP
259 ppmod = 0;
260#elif CONFIG_LPT_MODE_EPP_19_AND_SPP
261 ppmod = 1;
262#elif CONFIG_LPT_MODE_ECP
263 ppmod = 2;
264#elif CONFIG_LPT_MODE_ECP_AND_EPP_19
265 ppmod = 3;
266#elif CONFIG_LPT_MODE_SPP
267 ppmod = 4;
268#elif CONFIG_LPT_MODE_EPP_17_AND_SPP
269 ppmod = 5;
270#elif CONFIG_LPT_MODE_ECP_AND_EPP_17
271 ppmod = 7;
272#else
273#error CONFIG_LPT_MODE error.
274#endif
275
276 /* Setup internal parallel port */
277 lpt_reg |= (LPT_INT_C << 28);
278 lpt_reg |= (LPT_INT_ACK_SET << 27);
279 lpt_reg |= (ppmod << 24);
280 lpt_reg |= (LPT_UE << 23);
281 lpt_reg |= (LPT_PDMAS << 22);
282 lpt_reg |= (LPT_DREQS << 20);
283 lpt_reg |= (irq_to_int_routing[CONFIG_LPT_IRQ] << 16);
284 lpt_reg |= (CONFIG_LPT_IO << 0);
285#endif // CONFIG_LPT_ENABLE
286 pci_write_config32(dev, SB_REG_IPPCR, lpt_reg);
287}
288
289#define SETUP_GPIO_ADDR(n) \
290 u32 cfg##n = (CONFIG_GPIO_P##n##_DIR_ADDR << 16) | (CONFIG_GPIO_P##n##_DATA_ADDR);\
291 outl(cfg##n, base + 4 + (n * 4));\
292 gpio_enable_mask |= (1 << n);
293
294#define INIT_GPIO(n) \
295 outb(CONFIG_GPIO_P##n##_INIT_DIR, CONFIG_GPIO_P##n##_DIR_ADDR);\
296 outb(CONFIG_GPIO_P##n##_INIT_DATA, CONFIG_GPIO_P##n##_DATA_ADDR);
297
298static void ex_sb_gpio_init(struct device *dev)
299{
300 const int base = 0xb00;
301 u32 gpio_enable_mask = 0;
302 /* S/B register 63h - 62h : GPIO Port Config IO Base Address */
303 pci_write_config16(dev, SB_REG_GPIO_CFG_IO_BASE, base | 1);
304 /* Set GPIO port 0~9 base address.
305 * Config Base + 04h, 08h, 0ch... : GPIO port 0~9 data/dir decode addr.
306 * Bit 31-16 : DBA, GPIO direction base address.
307 * Bit 15-0 : DPBA, GPIO data port base address.
308 * */
309#if CONFIG_GPIO_P0_ENABLE
310 SETUP_GPIO_ADDR(0)
311#endif
312#if CONFIG_GPIO_P1_ENABLE
313 SETUP_GPIO_ADDR(1)
314#endif
315#if CONFIG_GPIO_P2_ENABLE
316 SETUP_GPIO_ADDR(2)
317#endif
318#if CONFIG_GPIO_P3_ENABLE
319 SETUP_GPIO_ADDR(3)
320#endif
321#if CONFIG_GPIO_P4_ENABLE
322 SETUP_GPIO_ADDR(4)
323#endif
324#if CONFIG_GPIO_P5_ENABLE
325 SETUP_GPIO_ADDR(5)
326#endif
327#if CONFIG_GPIO_P6_ENABLE
328 SETUP_GPIO_ADDR(6)
329#endif
330#if CONFIG_GPIO_P7_ENABLE
331 SETUP_GPIO_ADDR(7)
332#endif
333#if CONFIG_GPIO_P8_ENABLE
334 SETUP_GPIO_ADDR(8)
335#endif
336#if CONFIG_GPIO_P9_ENABLE
337 SETUP_GPIO_ADDR(9)
338#endif
339 /* Enable GPIO port 0~9. */
340 outl(gpio_enable_mask, base);
341 /* Set GPIO port 0-9 initial dir and data. */
342#if CONFIG_GPIO_P0_ENABLE
343 INIT_GPIO(0)
344#endif
345#if CONFIG_GPIO_P1_ENABLE
346 INIT_GPIO(1)
347#endif
348#if CONFIG_GPIO_P2_ENABLE
349 INIT_GPIO(2)
350#endif
351#if CONFIG_GPIO_P3_ENABLE
352 INIT_GPIO(3)
353#endif
354#if CONFIG_GPIO_P4_ENABLE
355 INIT_GPIO(4)
356#endif
357#if CONFIG_GPIO_P5_ENABLE
358 INIT_GPIO(5)
359#endif
360#if CONFIG_GPIO_P6_ENABLE
361 INIT_GPIO(6)
362#endif
363#if CONFIG_GPIO_P7_ENABLE
364 INIT_GPIO(7)
365#endif
366#if CONFIG_GPIO_P8_ENABLE
367 INIT_GPIO(8)
368#endif
369#if CONFIG_GPIO_P9_ENABLE
370 INIT_GPIO(9)
371#endif
372 /* Disable GPIO Port Config IO Base Address. */
373 pci_write_config16(dev, SB_REG_GPIO_CFG_IO_BASE, 0x0);
374}
375
376static u32 make_uart_config(u16 base, u8 irq)
377{
378 u8 mapped_irq = irq_to_int_routing[irq];
379 u32 cfg = 0;
380 cfg |= 1 << 23; // UE = enabled.
381 cfg |= (mapped_irq << 16); // UIRT.
382 cfg |= base; // UIOA.
383 return cfg;
384}
385
386#define SETUP_UART(n) \
387 uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\
388 outl(uart_cfg, base + (n - 1) * 4);\
389 uart8250_init(CONFIG_UART##n##_IO, 115200 / CONFIG_UART##n##_BAUD);
390
391static void ex_sb_uart_init(struct device *dev)
392{
393 const int base = 0xc00;
394 u32 uart_cfg = 0;
395 /* S/B register 61h - 60h : UART Config IO Base Address */
396 pci_write_config16(dev, SB_REG_UART_CFG_IO_BASE, base | 1);
397 /* setup UART */
398#if CONFIG_UART1_ENABLE
399 SETUP_UART(1)
400#endif
401#if CONFIG_UART2_ENABLE
402 SETUP_UART(2)
403#endif
404#if CONFIG_UART3_ENABLE
405 SETUP_UART(3)
406#endif
407#if CONFIG_UART4_ENABLE
408 SETUP_UART(4)
409#endif
410#if CONFIG_UART5_ENABLE
411 SETUP_UART(5)
412#endif
413#if CONFIG_UART6_ENABLE
414 SETUP_UART(6)
415#endif
416#if CONFIG_UART7_ENABLE
417 SETUP_UART(7)
418#endif
419#if CONFIG_UART8_ENABLE
420 SETUP_UART(8)
421#endif
422#if CONFIG_UART9_ENABLE
423 SETUP_UART(9)
424#endif
425#if CONFIG_UART10_ENABLE
426 SETUP_UART(10)
427#endif
428 /* Keep UART Config I/O base address */
429 //pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0);
430}
431
432static int get_rtc_update_in_progress(void)
433{
434 if (cmos_read(RTC_REG_A) & RTC_UIP)
435 return 1;
436 return 0;
437}
438
439static void unsafe_read_cmos_rtc(u8 rtc[7])
440{
441 rtc[0] = cmos_read(RTC_CLK_ALTCENTURY);
442 rtc[1] = cmos_read(RTC_CLK_YEAR);
443 rtc[2] = cmos_read(RTC_CLK_MONTH);
444 rtc[3] = cmos_read(RTC_CLK_DAYOFMONTH);
445 rtc[4] = cmos_read(RTC_CLK_HOUR);
446 rtc[5] = cmos_read(RTC_CLK_MINUTE);
447 rtc[6] = cmos_read(RTC_CLK_SECOND);
448}
449
450static void read_cmos_rtc(u8 rtc[7])
451{
452 /* Read RTC twice and check update-in-progress flag, to make
453 * sure RTC is correct */
454 u8 rtc_old[7], rtc_new[7];
455 while (get_rtc_update_in_progress()) ;
456 unsafe_read_cmos_rtc(rtc_new);
457 do {
458 memcpy(rtc_old, rtc_new, 7);
459 while (get_rtc_update_in_progress()) ;
460 unsafe_read_cmos_rtc(rtc_new);
461 } while (memcmp(rtc_new, rtc_old, 7) != 0);
462}
463
464/*
465 * Convert a number in decimal format into the BCD format.
466 * Return 255 if not a valid BCD value.
467 */
468static u8 bcd2dec(u8 bcd)
469{
470 u8 h, l;
471 h = bcd >> 4;
472 l = bcd & 0xf;
473 if (h > 9 || l > 9)
474 return 255;
475 return h * 10 + l;
476}
477
478static void fix_cmos_rtc_time(void)
479{
480 /* Read RTC data. */
481 u8 rtc[7];
482 read_cmos_rtc(rtc);
483
484 /* Convert RTC from BCD format to binary. */
485 u8 bin_rtc[7];
486 int i;
487 for (i = 0; i < 8; i++) {
488 bin_rtc[i] = bcd2dec(rtc[i]);
489 }
490
491 /* If RTC date is invalid, fix it. */
492 if (bin_rtc[0] > 99 || bin_rtc[1] > 99 || bin_rtc[2] > 12 || bin_rtc[3] > 31) {
493 /* Set PC compatible timing mode. */
494 cmos_write(0x26, RTC_REG_A);
495 cmos_write(0x02, RTC_REG_B);
496 /* Now setup a default date 2008/08/08 08:08:08. */
497 cmos_write(0x8, RTC_CLK_SECOND);
498 cmos_write(0x8, RTC_CLK_MINUTE);
499 cmos_write(0x8, RTC_CLK_HOUR);
500 cmos_write(0x6, RTC_CLK_DAYOFWEEK); /* Friday */
501 cmos_write(0x8, RTC_CLK_DAYOFMONTH);
502 cmos_write(0x8, RTC_CLK_MONTH);
503 cmos_write(0x8, RTC_CLK_YEAR);
504 cmos_write(0x20, RTC_CLK_ALTCENTURY);
505 }
506}
507
Andrew Wufea5b502013-10-31 20:12:09 +0800508static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size)
Andrew Wu00bf6472013-06-26 21:24:59 +0800509{
510 struct resource *res;
Andrew Wufea5b502013-10-31 20:12:09 +0800511 res = new_resource(dev, index);
512 res->base = base;
513 res->size = size;
Andrew Wu00bf6472013-06-26 21:24:59 +0800514 res->limit = 0xffffUL;
515 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
516}
517
Andrew Wufea5b502013-10-31 20:12:09 +0800518static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size)
Andrew Wu00bf6472013-06-26 21:24:59 +0800519{
520 /* SPI flash is in topmost of 4G memory space */
521 struct resource *res;
Andrew Wufea5b502013-10-31 20:12:09 +0800522 res = new_resource(dev, index);
Andrew Wu00bf6472013-06-26 21:24:59 +0800523 res->base = 0x100000000LL - flash_size;
524 res->size = flash_size;
525 res->limit = 0xffffffffUL;
526 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
527}
528
529static void vortex86_sb_read_resources(device_t dev)
530{
531 u32 flash_size = 8 * 1024 * 1024;
532
533 pci_dev_read_resources(dev);
534
535 if (dev->device == 0x6011) {
536 /* It is EX CPU southbridge */
537 if (get_pci_dev_func(dev) != 0) {
538 /* only for function 0, skip function 1 */
539 return;
540 }
541 /* default SPI flash ROM is 64MB */
542 flash_size = 64 * 1024 * 1024;
543 }
544
Andrew Wufea5b502013-10-31 20:12:09 +0800545 /* Reserve space for legacy I/O */
546 vortex86_sb_set_io_resv(dev, 1, 0, 0x1000UL);
Andrew Wu00bf6472013-06-26 21:24:59 +0800547
548 /* Reserve space for flash */
Andrew Wufea5b502013-10-31 20:12:09 +0800549 vortex86_sb_set_spi_flash_size(dev, 2, flash_size);
Andrew Wu00bf6472013-06-26 21:24:59 +0800550}
551
Andrew Wu52914322013-07-09 21:29:25 +0800552static void southbridge_init_func1(struct device *dev)
553{
554 /* Handle S/B function 1 PCI IRQ routing. (SPI1/MOTOR) */
555 u32 ext_int_routing2 = 0;
556 /* Setup S/B function 1 PCI Extend Interrupt routing table reg 2(0xb4). */
557 ext_int_routing2 |= irq_to_int_routing[SPI1_IRQ] << SPI1_IRQ_SHIFT;
558 ext_int_routing2 |= irq_to_int_routing[MOTOR_IRQ] << MOTOR_IRQ_SHIFT;
559 pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2);
560
561 /* Assign in-chip PCI device IRQs. */
562 if (SPI1_IRQ || MOTOR_IRQ) {
563 unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 };
564 pci_assign_irqs(0, 0x10, irqs);
565 }
566}
567
Andrew Wu00bf6472013-06-26 21:24:59 +0800568static void southbridge_init(struct device *dev)
569{
Andrew Wu52914322013-07-09 21:29:25 +0800570 /* Check it is function 0 or 1. (Same Vendor/Device ID) */
571 if (get_pci_dev_func(dev) != 0) {
572 southbridge_init_func1(dev);
573 return;
Andrew Wu00bf6472013-06-26 21:24:59 +0800574 }
575 upload_dmp_keyboard_firmware(dev);
576 vortex_sb_init(dev);
577 if (dev->device == 0x6011) {
578 ex_sb_gpio_init(dev);
579 ex_sb_uart_init(dev);
580 }
581 pci_routing_fixup(dev);
582
583 fix_cmos_rtc_time();
584 rtc_init(0);
Andrew Wu1fefa842013-10-24 20:37:48 +0800585 /* Check keyboard controller ready. If timeout, reload firmware code
586 * and try again.
587 */
588 u32 retries = 10;
589 while (!kbc_wait_system_flag()) {
590 if (!retries) {
591 post_code(POST_DMP_KBD_IS_BAD);
592 die("The keyboard timeout occurred too often. "
593 "Your CPU is probably defect. "
594 "Contact your dealer to replace it\n");
595 }
596 upload_dmp_keyboard_firmware(dev);
597 retries--;
598 }
599 post_code(POST_DMP_KBD_IS_READY);
Andrew Wu3fa1a132013-10-09 18:57:20 +0800600 pc_keyboard_init(0);
Andrew Wu00bf6472013-06-26 21:24:59 +0800601}
602
603static struct device_operations vortex_sb_ops = {
604 .read_resources = vortex86_sb_read_resources,
605 .set_resources = pci_dev_set_resources,
606 .enable_resources = pci_dev_enable_resources,
607 .init = &southbridge_init,
608 .scan_bus = scan_static_bus,
609 .enable = 0,
610 .ops_pci = 0,
611};
612
613static const struct pci_driver pci_driver_6011 __pci_driver = {
614 .ops = &vortex_sb_ops,
615 .vendor = PCI_VENDOR_ID_RDC,
616 .device = 0x6011, /* EX CPU S/B ID */
617};
618
619struct chip_operations southbridge_dmp_vortex86ex_ops = {
620 CHIP_NAME("DMP Vortex86EX Southbridge")
621 .enable_dev = 0
622};